1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-ep93xx/include/mach/hardware.h 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ASM_ARCH_HARDWARE_H 7*4882a593Smuzhiyun #define __ASM_ARCH_HARDWARE_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "platform.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * The EP93xx has two external crystal oscillators. To generate the 13*4882a593Smuzhiyun * required high-frequency clocks, the processor uses two phase-locked- 14*4882a593Smuzhiyun * loops (PLLs) to multiply the incoming external clock signal to much 15*4882a593Smuzhiyun * higher frequencies that are then divided down by programmable dividers 16*4882a593Smuzhiyun * to produce the needed clocks. The PLLs operate independently of one 17*4882a593Smuzhiyun * another. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define EP93XX_EXT_CLK_RATE 14745600 20*4882a593Smuzhiyun #define EP93XX_EXT_RTC_RATE 32768 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4) 23*4882a593Smuzhiyun #define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif 26