1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Include file for the EP93XX GPIO controller machine specifics */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __GPIO_EP93XX_H 5*4882a593Smuzhiyun #define __GPIO_EP93XX_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <mach/ep93xx-regs.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000) 10*4882a593Smuzhiyun #define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000) 11*4882a593Smuzhiyun #define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) 12*4882a593Smuzhiyun #define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) 13*4882a593Smuzhiyun #define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) 14*4882a593Smuzhiyun #define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) 15*4882a593Smuzhiyun #define EP93XX_GPIO_EEDRIVE EP93XX_GPIO_REG(0xc8) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* GPIO port A. */ 18*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_A(x) ((x) + 0) 19*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0) 20*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO1 EP93XX_GPIO_LINE_A(1) 21*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO2 EP93XX_GPIO_LINE_A(2) 22*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO3 EP93XX_GPIO_LINE_A(3) 23*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO4 EP93XX_GPIO_LINE_A(4) 24*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO5 EP93XX_GPIO_LINE_A(5) 25*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO6 EP93XX_GPIO_LINE_A(6) 26*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO7 EP93XX_GPIO_LINE_A(7) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* GPIO port B. */ 29*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_B(x) ((x) + 8) 30*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO8 EP93XX_GPIO_LINE_B(0) 31*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO9 EP93XX_GPIO_LINE_B(1) 32*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO10 EP93XX_GPIO_LINE_B(2) 33*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO11 EP93XX_GPIO_LINE_B(3) 34*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO12 EP93XX_GPIO_LINE_B(4) 35*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO13 EP93XX_GPIO_LINE_B(5) 36*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO14 EP93XX_GPIO_LINE_B(6) 37*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EGPIO15 EP93XX_GPIO_LINE_B(7) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* GPIO port C. */ 40*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_C(x) ((x) + 40) 41*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_ROW0 EP93XX_GPIO_LINE_C(0) 42*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_ROW1 EP93XX_GPIO_LINE_C(1) 43*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_ROW2 EP93XX_GPIO_LINE_C(2) 44*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_ROW3 EP93XX_GPIO_LINE_C(3) 45*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_ROW4 EP93XX_GPIO_LINE_C(4) 46*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_ROW5 EP93XX_GPIO_LINE_C(5) 47*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_ROW6 EP93XX_GPIO_LINE_C(6) 48*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_ROW7 EP93XX_GPIO_LINE_C(7) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* GPIO port D. */ 51*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_D(x) ((x) + 24) 52*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_COL0 EP93XX_GPIO_LINE_D(0) 53*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_COL1 EP93XX_GPIO_LINE_D(1) 54*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_COL2 EP93XX_GPIO_LINE_D(2) 55*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_COL3 EP93XX_GPIO_LINE_D(3) 56*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_COL4 EP93XX_GPIO_LINE_D(4) 57*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_COL5 EP93XX_GPIO_LINE_D(5) 58*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_COL6 EP93XX_GPIO_LINE_D(6) 59*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_COL7 EP93XX_GPIO_LINE_D(7) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* GPIO port E. */ 62*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_E(x) ((x) + 32) 63*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_GRLED EP93XX_GPIO_LINE_E(0) 64*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_RDLED EP93XX_GPIO_LINE_E(1) 65*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_DIORn EP93XX_GPIO_LINE_E(2) 66*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_IDECS1n EP93XX_GPIO_LINE_E(3) 67*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_IDECS2n EP93XX_GPIO_LINE_E(4) 68*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_IDEDA0 EP93XX_GPIO_LINE_E(5) 69*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_IDEDA1 EP93XX_GPIO_LINE_E(6) 70*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_IDEDA2 EP93XX_GPIO_LINE_E(7) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* GPIO port F. */ 73*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_F(x) ((x) + 16) 74*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_WP EP93XX_GPIO_LINE_F(0) 75*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_MCCD1 EP93XX_GPIO_LINE_F(1) 76*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_MCCD2 EP93XX_GPIO_LINE_F(2) 77*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_MCBVD1 EP93XX_GPIO_LINE_F(3) 78*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_MCBVD2 EP93XX_GPIO_LINE_F(4) 79*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_VS1 EP93XX_GPIO_LINE_F(5) 80*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_READY EP93XX_GPIO_LINE_F(6) 81*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_VS2 EP93XX_GPIO_LINE_F(7) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* GPIO port G. */ 84*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_G(x) ((x) + 48) 85*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EECLK EP93XX_GPIO_LINE_G(0) 86*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_EEDAT EP93XX_GPIO_LINE_G(1) 87*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_SLA0 EP93XX_GPIO_LINE_G(2) 88*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_SLA1 EP93XX_GPIO_LINE_G(3) 89*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_DD12 EP93XX_GPIO_LINE_G(4) 90*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_DD13 EP93XX_GPIO_LINE_G(5) 91*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_DD14 EP93XX_GPIO_LINE_G(6) 92*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_DD15 EP93XX_GPIO_LINE_G(7) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* GPIO port H. */ 95*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_H(x) ((x) + 56) 96*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_DD0 EP93XX_GPIO_LINE_H(0) 97*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_DD1 EP93XX_GPIO_LINE_H(1) 98*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_DD2 EP93XX_GPIO_LINE_H(2) 99*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_DD3 EP93XX_GPIO_LINE_H(3) 100*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_DD4 EP93XX_GPIO_LINE_H(4) 101*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_DD5 EP93XX_GPIO_LINE_H(5) 102*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_DD6 EP93XX_GPIO_LINE_H(6) 103*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_DD7 EP93XX_GPIO_LINE_H(7) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* maximum value for gpio line identifiers */ 106*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_MAX EP93XX_GPIO_LINE_H(7) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* maximum value for irq capable line identifiers */ 109*4882a593Smuzhiyun #define EP93XX_GPIO_LINE_MAX_IRQ EP93XX_GPIO_LINE_F(7) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #endif /* __GPIO_EP93XX_H */ 112