1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/mach-ep93xx/core.c
4*4882a593Smuzhiyun * Core routines for Cirrus EP93xx chips.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
7*4882a593Smuzhiyun * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Thanks go to Michael Burian and Ray Lehtiniemi for their key
10*4882a593Smuzhiyun * role in the ep93xx linux community.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/platform_device.h>
18*4882a593Smuzhiyun #include <linux/interrupt.h>
19*4882a593Smuzhiyun #include <linux/dma-mapping.h>
20*4882a593Smuzhiyun #include <linux/sys_soc.h>
21*4882a593Smuzhiyun #include <linux/irq.h>
22*4882a593Smuzhiyun #include <linux/io.h>
23*4882a593Smuzhiyun #include <linux/gpio.h>
24*4882a593Smuzhiyun #include <linux/leds.h>
25*4882a593Smuzhiyun #include <linux/termios.h>
26*4882a593Smuzhiyun #include <linux/amba/bus.h>
27*4882a593Smuzhiyun #include <linux/amba/serial.h>
28*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
29*4882a593Smuzhiyun #include <linux/i2c.h>
30*4882a593Smuzhiyun #include <linux/gpio/machine.h>
31*4882a593Smuzhiyun #include <linux/spi/spi.h>
32*4882a593Smuzhiyun #include <linux/export.h>
33*4882a593Smuzhiyun #include <linux/irqchip/arm-vic.h>
34*4882a593Smuzhiyun #include <linux/reboot.h>
35*4882a593Smuzhiyun #include <linux/usb/ohci_pdriver.h>
36*4882a593Smuzhiyun #include <linux/random.h>
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #include "hardware.h"
39*4882a593Smuzhiyun #include <linux/platform_data/video-ep93xx.h>
40*4882a593Smuzhiyun #include <linux/platform_data/keypad-ep93xx.h>
41*4882a593Smuzhiyun #include <linux/platform_data/spi-ep93xx.h>
42*4882a593Smuzhiyun #include <linux/soc/cirrus/ep93xx.h>
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #include "gpio-ep93xx.h"
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #include <asm/mach/arch.h>
47*4882a593Smuzhiyun #include <asm/mach/map.h>
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #include "soc.h"
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /*************************************************************************
52*4882a593Smuzhiyun * Static I/O mappings that are needed for all EP93xx platforms
53*4882a593Smuzhiyun *************************************************************************/
54*4882a593Smuzhiyun static struct map_desc ep93xx_io_desc[] __initdata = {
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun .virtual = EP93XX_AHB_VIRT_BASE,
57*4882a593Smuzhiyun .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
58*4882a593Smuzhiyun .length = EP93XX_AHB_SIZE,
59*4882a593Smuzhiyun .type = MT_DEVICE,
60*4882a593Smuzhiyun }, {
61*4882a593Smuzhiyun .virtual = EP93XX_APB_VIRT_BASE,
62*4882a593Smuzhiyun .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
63*4882a593Smuzhiyun .length = EP93XX_APB_SIZE,
64*4882a593Smuzhiyun .type = MT_DEVICE,
65*4882a593Smuzhiyun },
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
ep93xx_map_io(void)68*4882a593Smuzhiyun void __init ep93xx_map_io(void)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /*************************************************************************
74*4882a593Smuzhiyun * EP93xx IRQ handling
75*4882a593Smuzhiyun *************************************************************************/
ep93xx_init_irq(void)76*4882a593Smuzhiyun void __init ep93xx_init_irq(void)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
79*4882a593Smuzhiyun vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /*************************************************************************
84*4882a593Smuzhiyun * EP93xx System Controller Software Locked register handling
85*4882a593Smuzhiyun *************************************************************************/
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /*
88*4882a593Smuzhiyun * syscon_swlock prevents anything else from writing to the syscon
89*4882a593Smuzhiyun * block while a software locked register is being written.
90*4882a593Smuzhiyun */
91*4882a593Smuzhiyun static DEFINE_SPINLOCK(syscon_swlock);
92*4882a593Smuzhiyun
ep93xx_syscon_swlocked_write(unsigned int val,void __iomem * reg)93*4882a593Smuzhiyun void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun unsigned long flags;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun spin_lock_irqsave(&syscon_swlock, flags);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
100*4882a593Smuzhiyun __raw_writel(val, reg);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun spin_unlock_irqrestore(&syscon_swlock, flags);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
ep93xx_devcfg_set_clear(unsigned int set_bits,unsigned int clear_bits)105*4882a593Smuzhiyun void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun unsigned long flags;
108*4882a593Smuzhiyun unsigned int val;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun spin_lock_irqsave(&syscon_swlock, flags);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun val = __raw_readl(EP93XX_SYSCON_DEVCFG);
113*4882a593Smuzhiyun val &= ~clear_bits;
114*4882a593Smuzhiyun val |= set_bits;
115*4882a593Smuzhiyun __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
116*4882a593Smuzhiyun __raw_writel(val, EP93XX_SYSCON_DEVCFG);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun spin_unlock_irqrestore(&syscon_swlock, flags);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /**
122*4882a593Smuzhiyun * ep93xx_chip_revision() - returns the EP93xx chip revision
123*4882a593Smuzhiyun *
124*4882a593Smuzhiyun * See "platform.h" for more information.
125*4882a593Smuzhiyun */
ep93xx_chip_revision(void)126*4882a593Smuzhiyun unsigned int ep93xx_chip_revision(void)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun unsigned int v;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun v = __raw_readl(EP93XX_SYSCON_SYSCFG);
131*4882a593Smuzhiyun v &= EP93XX_SYSCON_SYSCFG_REV_MASK;
132*4882a593Smuzhiyun v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT;
133*4882a593Smuzhiyun return v;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ep93xx_chip_revision);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /*************************************************************************
138*4882a593Smuzhiyun * EP93xx GPIO
139*4882a593Smuzhiyun *************************************************************************/
140*4882a593Smuzhiyun static struct resource ep93xx_gpio_resource[] = {
141*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc),
142*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB),
143*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_GPIO0MUX),
144*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_GPIO1MUX),
145*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_GPIO2MUX),
146*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_GPIO3MUX),
147*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_GPIO4MUX),
148*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_GPIO5MUX),
149*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_GPIO6MUX),
150*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_GPIO7MUX),
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun static struct platform_device ep93xx_gpio_device = {
154*4882a593Smuzhiyun .name = "gpio-ep93xx",
155*4882a593Smuzhiyun .id = -1,
156*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_gpio_resource),
157*4882a593Smuzhiyun .resource = ep93xx_gpio_resource,
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /*************************************************************************
161*4882a593Smuzhiyun * EP93xx peripheral handling
162*4882a593Smuzhiyun *************************************************************************/
163*4882a593Smuzhiyun #define EP93XX_UART_MCR_OFFSET (0x0100)
164*4882a593Smuzhiyun
ep93xx_uart_set_mctrl(struct amba_device * dev,void __iomem * base,unsigned int mctrl)165*4882a593Smuzhiyun static void ep93xx_uart_set_mctrl(struct amba_device *dev,
166*4882a593Smuzhiyun void __iomem *base, unsigned int mctrl)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun unsigned int mcr;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun mcr = 0;
171*4882a593Smuzhiyun if (mctrl & TIOCM_RTS)
172*4882a593Smuzhiyun mcr |= 2;
173*4882a593Smuzhiyun if (mctrl & TIOCM_DTR)
174*4882a593Smuzhiyun mcr |= 1;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun static struct amba_pl010_data ep93xx_uart_data = {
180*4882a593Smuzhiyun .set_mctrl = ep93xx_uart_set_mctrl,
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE,
184*4882a593Smuzhiyun { IRQ_EP93XX_UART1 }, &ep93xx_uart_data);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE,
187*4882a593Smuzhiyun { IRQ_EP93XX_UART2 }, NULL);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
190*4882a593Smuzhiyun { IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun static struct resource ep93xx_rtc_resource[] = {
193*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c),
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun static struct platform_device ep93xx_rtc_device = {
197*4882a593Smuzhiyun .name = "ep93xx-rtc",
198*4882a593Smuzhiyun .id = -1,
199*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_rtc_resource),
200*4882a593Smuzhiyun .resource = ep93xx_rtc_resource,
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun /*************************************************************************
204*4882a593Smuzhiyun * EP93xx OHCI USB Host
205*4882a593Smuzhiyun *************************************************************************/
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun static struct clk *ep93xx_ohci_host_clock;
208*4882a593Smuzhiyun
ep93xx_ohci_power_on(struct platform_device * pdev)209*4882a593Smuzhiyun static int ep93xx_ohci_power_on(struct platform_device *pdev)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun if (!ep93xx_ohci_host_clock) {
212*4882a593Smuzhiyun ep93xx_ohci_host_clock = devm_clk_get(&pdev->dev, NULL);
213*4882a593Smuzhiyun if (IS_ERR(ep93xx_ohci_host_clock))
214*4882a593Smuzhiyun return PTR_ERR(ep93xx_ohci_host_clock);
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun return clk_enable(ep93xx_ohci_host_clock);
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
ep93xx_ohci_power_off(struct platform_device * pdev)220*4882a593Smuzhiyun static void ep93xx_ohci_power_off(struct platform_device *pdev)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun clk_disable(ep93xx_ohci_host_clock);
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun static struct usb_ohci_pdata ep93xx_ohci_pdata = {
226*4882a593Smuzhiyun .power_on = ep93xx_ohci_power_on,
227*4882a593Smuzhiyun .power_off = ep93xx_ohci_power_off,
228*4882a593Smuzhiyun .power_suspend = ep93xx_ohci_power_off,
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun static struct resource ep93xx_ohci_resources[] = {
232*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000),
233*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_USB),
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun static u64 ep93xx_ohci_dma_mask = DMA_BIT_MASK(32);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun static struct platform_device ep93xx_ohci_device = {
239*4882a593Smuzhiyun .name = "ohci-platform",
240*4882a593Smuzhiyun .id = -1,
241*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
242*4882a593Smuzhiyun .resource = ep93xx_ohci_resources,
243*4882a593Smuzhiyun .dev = {
244*4882a593Smuzhiyun .dma_mask = &ep93xx_ohci_dma_mask,
245*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
246*4882a593Smuzhiyun .platform_data = &ep93xx_ohci_pdata,
247*4882a593Smuzhiyun },
248*4882a593Smuzhiyun };
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun /*************************************************************************
251*4882a593Smuzhiyun * EP93xx physmap'ed flash
252*4882a593Smuzhiyun *************************************************************************/
253*4882a593Smuzhiyun static struct physmap_flash_data ep93xx_flash_data;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun static struct resource ep93xx_flash_resource = {
256*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
257*4882a593Smuzhiyun };
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun static struct platform_device ep93xx_flash = {
260*4882a593Smuzhiyun .name = "physmap-flash",
261*4882a593Smuzhiyun .id = 0,
262*4882a593Smuzhiyun .dev = {
263*4882a593Smuzhiyun .platform_data = &ep93xx_flash_data,
264*4882a593Smuzhiyun },
265*4882a593Smuzhiyun .num_resources = 1,
266*4882a593Smuzhiyun .resource = &ep93xx_flash_resource,
267*4882a593Smuzhiyun };
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun /**
270*4882a593Smuzhiyun * ep93xx_register_flash() - Register the external flash device.
271*4882a593Smuzhiyun * @width: bank width in octets
272*4882a593Smuzhiyun * @start: resource start address
273*4882a593Smuzhiyun * @size: resource size
274*4882a593Smuzhiyun */
ep93xx_register_flash(unsigned int width,resource_size_t start,resource_size_t size)275*4882a593Smuzhiyun void __init ep93xx_register_flash(unsigned int width,
276*4882a593Smuzhiyun resource_size_t start, resource_size_t size)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun ep93xx_flash_data.width = width;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun ep93xx_flash_resource.start = start;
281*4882a593Smuzhiyun ep93xx_flash_resource.end = start + size - 1;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun platform_device_register(&ep93xx_flash);
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun /*************************************************************************
288*4882a593Smuzhiyun * EP93xx ethernet peripheral handling
289*4882a593Smuzhiyun *************************************************************************/
290*4882a593Smuzhiyun static struct ep93xx_eth_data ep93xx_eth_data;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun static struct resource ep93xx_eth_resource[] = {
293*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000),
294*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET),
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32);
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun static struct platform_device ep93xx_eth_device = {
300*4882a593Smuzhiyun .name = "ep93xx-eth",
301*4882a593Smuzhiyun .id = -1,
302*4882a593Smuzhiyun .dev = {
303*4882a593Smuzhiyun .platform_data = &ep93xx_eth_data,
304*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
305*4882a593Smuzhiyun .dma_mask = &ep93xx_eth_dma_mask,
306*4882a593Smuzhiyun },
307*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_eth_resource),
308*4882a593Smuzhiyun .resource = ep93xx_eth_resource,
309*4882a593Smuzhiyun };
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun /**
312*4882a593Smuzhiyun * ep93xx_register_eth - Register the built-in ethernet platform device.
313*4882a593Smuzhiyun * @data: platform specific ethernet configuration (__initdata)
314*4882a593Smuzhiyun * @copy_addr: flag indicating that the MAC address should be copied
315*4882a593Smuzhiyun * from the IndAd registers (as programmed by the bootloader)
316*4882a593Smuzhiyun */
ep93xx_register_eth(struct ep93xx_eth_data * data,int copy_addr)317*4882a593Smuzhiyun void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
318*4882a593Smuzhiyun {
319*4882a593Smuzhiyun if (copy_addr)
320*4882a593Smuzhiyun memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun ep93xx_eth_data = *data;
323*4882a593Smuzhiyun platform_device_register(&ep93xx_eth_device);
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun /*************************************************************************
328*4882a593Smuzhiyun * EP93xx i2c peripheral handling
329*4882a593Smuzhiyun *************************************************************************/
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun /* All EP93xx devices use the same two GPIO pins for I2C bit-banging */
332*4882a593Smuzhiyun static struct gpiod_lookup_table ep93xx_i2c_gpiod_table = {
333*4882a593Smuzhiyun .dev_id = "i2c-gpio.0",
334*4882a593Smuzhiyun .table = {
335*4882a593Smuzhiyun /* Use local offsets on gpiochip/port "G" */
336*4882a593Smuzhiyun GPIO_LOOKUP_IDX("G", 1, NULL, 0,
337*4882a593Smuzhiyun GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
338*4882a593Smuzhiyun GPIO_LOOKUP_IDX("G", 0, NULL, 1,
339*4882a593Smuzhiyun GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
340*4882a593Smuzhiyun },
341*4882a593Smuzhiyun };
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun static struct platform_device ep93xx_i2c_device = {
344*4882a593Smuzhiyun .name = "i2c-gpio",
345*4882a593Smuzhiyun .id = 0,
346*4882a593Smuzhiyun .dev = {
347*4882a593Smuzhiyun .platform_data = NULL,
348*4882a593Smuzhiyun },
349*4882a593Smuzhiyun };
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun /**
352*4882a593Smuzhiyun * ep93xx_register_i2c - Register the i2c platform device.
353*4882a593Smuzhiyun * @devices: platform specific i2c bus device information (__initdata)
354*4882a593Smuzhiyun * @num: the number of devices on the i2c bus
355*4882a593Smuzhiyun */
ep93xx_register_i2c(struct i2c_board_info * devices,int num)356*4882a593Smuzhiyun void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun /*
359*4882a593Smuzhiyun * FIXME: this just sets the two pins as non-opendrain, as no
360*4882a593Smuzhiyun * platforms tries to do that anyway. Flag the applicable lines
361*4882a593Smuzhiyun * as open drain in the GPIO_LOOKUP above and the driver or
362*4882a593Smuzhiyun * gpiolib will handle open drain/open drain emulation as need
363*4882a593Smuzhiyun * be. Right now i2c-gpio emulates open drain which is not
364*4882a593Smuzhiyun * optimal.
365*4882a593Smuzhiyun */
366*4882a593Smuzhiyun __raw_writel((0 << 1) | (0 << 0),
367*4882a593Smuzhiyun EP93XX_GPIO_EEDRIVE);
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun i2c_register_board_info(0, devices, num);
370*4882a593Smuzhiyun gpiod_add_lookup_table(&ep93xx_i2c_gpiod_table);
371*4882a593Smuzhiyun platform_device_register(&ep93xx_i2c_device);
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun /*************************************************************************
375*4882a593Smuzhiyun * EP93xx SPI peripheral handling
376*4882a593Smuzhiyun *************************************************************************/
377*4882a593Smuzhiyun static struct ep93xx_spi_info ep93xx_spi_master_data;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun static struct resource ep93xx_spi_resources[] = {
380*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18),
381*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_SSP),
382*4882a593Smuzhiyun };
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun static struct platform_device ep93xx_spi_device = {
387*4882a593Smuzhiyun .name = "ep93xx-spi",
388*4882a593Smuzhiyun .id = 0,
389*4882a593Smuzhiyun .dev = {
390*4882a593Smuzhiyun .platform_data = &ep93xx_spi_master_data,
391*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
392*4882a593Smuzhiyun .dma_mask = &ep93xx_spi_dma_mask,
393*4882a593Smuzhiyun },
394*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_spi_resources),
395*4882a593Smuzhiyun .resource = ep93xx_spi_resources,
396*4882a593Smuzhiyun };
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun /**
399*4882a593Smuzhiyun * ep93xx_register_spi() - registers spi platform device
400*4882a593Smuzhiyun * @info: ep93xx board specific spi master info (__initdata)
401*4882a593Smuzhiyun * @devices: SPI devices to register (__initdata)
402*4882a593Smuzhiyun * @num: number of SPI devices to register
403*4882a593Smuzhiyun *
404*4882a593Smuzhiyun * This function registers platform device for the EP93xx SPI controller and
405*4882a593Smuzhiyun * also makes sure that SPI pins are muxed so that I2S is not using those pins.
406*4882a593Smuzhiyun */
ep93xx_register_spi(struct ep93xx_spi_info * info,struct spi_board_info * devices,int num)407*4882a593Smuzhiyun void __init ep93xx_register_spi(struct ep93xx_spi_info *info,
408*4882a593Smuzhiyun struct spi_board_info *devices, int num)
409*4882a593Smuzhiyun {
410*4882a593Smuzhiyun /*
411*4882a593Smuzhiyun * When SPI is used, we need to make sure that I2S is muxed off from
412*4882a593Smuzhiyun * SPI pins.
413*4882a593Smuzhiyun */
414*4882a593Smuzhiyun ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP);
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun ep93xx_spi_master_data = *info;
417*4882a593Smuzhiyun spi_register_board_info(devices, num);
418*4882a593Smuzhiyun platform_device_register(&ep93xx_spi_device);
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun /*************************************************************************
422*4882a593Smuzhiyun * EP93xx LEDs
423*4882a593Smuzhiyun *************************************************************************/
424*4882a593Smuzhiyun static const struct gpio_led ep93xx_led_pins[] __initconst = {
425*4882a593Smuzhiyun {
426*4882a593Smuzhiyun .name = "platform:grled",
427*4882a593Smuzhiyun .gpio = EP93XX_GPIO_LINE_GRLED,
428*4882a593Smuzhiyun }, {
429*4882a593Smuzhiyun .name = "platform:rdled",
430*4882a593Smuzhiyun .gpio = EP93XX_GPIO_LINE_RDLED,
431*4882a593Smuzhiyun },
432*4882a593Smuzhiyun };
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun static const struct gpio_led_platform_data ep93xx_led_data __initconst = {
435*4882a593Smuzhiyun .num_leds = ARRAY_SIZE(ep93xx_led_pins),
436*4882a593Smuzhiyun .leds = ep93xx_led_pins,
437*4882a593Smuzhiyun };
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun /*************************************************************************
440*4882a593Smuzhiyun * EP93xx pwm peripheral handling
441*4882a593Smuzhiyun *************************************************************************/
442*4882a593Smuzhiyun static struct resource ep93xx_pwm0_resource[] = {
443*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10),
444*4882a593Smuzhiyun };
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun static struct platform_device ep93xx_pwm0_device = {
447*4882a593Smuzhiyun .name = "ep93xx-pwm",
448*4882a593Smuzhiyun .id = 0,
449*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_pwm0_resource),
450*4882a593Smuzhiyun .resource = ep93xx_pwm0_resource,
451*4882a593Smuzhiyun };
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun static struct resource ep93xx_pwm1_resource[] = {
454*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10),
455*4882a593Smuzhiyun };
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun static struct platform_device ep93xx_pwm1_device = {
458*4882a593Smuzhiyun .name = "ep93xx-pwm",
459*4882a593Smuzhiyun .id = 1,
460*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_pwm1_resource),
461*4882a593Smuzhiyun .resource = ep93xx_pwm1_resource,
462*4882a593Smuzhiyun };
463*4882a593Smuzhiyun
ep93xx_register_pwm(int pwm0,int pwm1)464*4882a593Smuzhiyun void __init ep93xx_register_pwm(int pwm0, int pwm1)
465*4882a593Smuzhiyun {
466*4882a593Smuzhiyun if (pwm0)
467*4882a593Smuzhiyun platform_device_register(&ep93xx_pwm0_device);
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
470*4882a593Smuzhiyun if (pwm1)
471*4882a593Smuzhiyun platform_device_register(&ep93xx_pwm1_device);
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
ep93xx_pwm_acquire_gpio(struct platform_device * pdev)474*4882a593Smuzhiyun int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
475*4882a593Smuzhiyun {
476*4882a593Smuzhiyun int err;
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun if (pdev->id == 0) {
479*4882a593Smuzhiyun err = 0;
480*4882a593Smuzhiyun } else if (pdev->id == 1) {
481*4882a593Smuzhiyun err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
482*4882a593Smuzhiyun dev_name(&pdev->dev));
483*4882a593Smuzhiyun if (err)
484*4882a593Smuzhiyun return err;
485*4882a593Smuzhiyun err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
486*4882a593Smuzhiyun if (err)
487*4882a593Smuzhiyun goto fail;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun /* PWM 1 output on EGPIO[14] */
490*4882a593Smuzhiyun ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
491*4882a593Smuzhiyun } else {
492*4882a593Smuzhiyun err = -ENODEV;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun return err;
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun fail:
498*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_EGPIO14);
499*4882a593Smuzhiyun return err;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
502*4882a593Smuzhiyun
ep93xx_pwm_release_gpio(struct platform_device * pdev)503*4882a593Smuzhiyun void ep93xx_pwm_release_gpio(struct platform_device *pdev)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun if (pdev->id == 1) {
506*4882a593Smuzhiyun gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
507*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_EGPIO14);
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun /* EGPIO[14] used for GPIO */
510*4882a593Smuzhiyun ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun /*************************************************************************
517*4882a593Smuzhiyun * EP93xx video peripheral handling
518*4882a593Smuzhiyun *************************************************************************/
519*4882a593Smuzhiyun static struct ep93xxfb_mach_info ep93xxfb_data;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun static struct resource ep93xx_fb_resource[] = {
522*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800),
523*4882a593Smuzhiyun };
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun static struct platform_device ep93xx_fb_device = {
526*4882a593Smuzhiyun .name = "ep93xx-fb",
527*4882a593Smuzhiyun .id = -1,
528*4882a593Smuzhiyun .dev = {
529*4882a593Smuzhiyun .platform_data = &ep93xxfb_data,
530*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
531*4882a593Smuzhiyun .dma_mask = &ep93xx_fb_device.dev.coherent_dma_mask,
532*4882a593Smuzhiyun },
533*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_fb_resource),
534*4882a593Smuzhiyun .resource = ep93xx_fb_resource,
535*4882a593Smuzhiyun };
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun /* The backlight use a single register in the framebuffer's register space */
538*4882a593Smuzhiyun #define EP93XX_RASTER_REG_BRIGHTNESS 0x20
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun static struct resource ep93xx_bl_resources[] = {
541*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE +
542*4882a593Smuzhiyun EP93XX_RASTER_REG_BRIGHTNESS, 0x04),
543*4882a593Smuzhiyun };
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun static struct platform_device ep93xx_bl_device = {
546*4882a593Smuzhiyun .name = "ep93xx-bl",
547*4882a593Smuzhiyun .id = -1,
548*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_bl_resources),
549*4882a593Smuzhiyun .resource = ep93xx_bl_resources,
550*4882a593Smuzhiyun };
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun /**
553*4882a593Smuzhiyun * ep93xx_register_fb - Register the framebuffer platform device.
554*4882a593Smuzhiyun * @data: platform specific framebuffer configuration (__initdata)
555*4882a593Smuzhiyun */
ep93xx_register_fb(struct ep93xxfb_mach_info * data)556*4882a593Smuzhiyun void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
557*4882a593Smuzhiyun {
558*4882a593Smuzhiyun ep93xxfb_data = *data;
559*4882a593Smuzhiyun platform_device_register(&ep93xx_fb_device);
560*4882a593Smuzhiyun platform_device_register(&ep93xx_bl_device);
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun /*************************************************************************
565*4882a593Smuzhiyun * EP93xx matrix keypad peripheral handling
566*4882a593Smuzhiyun *************************************************************************/
567*4882a593Smuzhiyun static struct ep93xx_keypad_platform_data ep93xx_keypad_data;
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun static struct resource ep93xx_keypad_resource[] = {
570*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c),
571*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_KEY),
572*4882a593Smuzhiyun };
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun static struct platform_device ep93xx_keypad_device = {
575*4882a593Smuzhiyun .name = "ep93xx-keypad",
576*4882a593Smuzhiyun .id = -1,
577*4882a593Smuzhiyun .dev = {
578*4882a593Smuzhiyun .platform_data = &ep93xx_keypad_data,
579*4882a593Smuzhiyun },
580*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_keypad_resource),
581*4882a593Smuzhiyun .resource = ep93xx_keypad_resource,
582*4882a593Smuzhiyun };
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun /**
585*4882a593Smuzhiyun * ep93xx_register_keypad - Register the keypad platform device.
586*4882a593Smuzhiyun * @data: platform specific keypad configuration (__initdata)
587*4882a593Smuzhiyun */
ep93xx_register_keypad(struct ep93xx_keypad_platform_data * data)588*4882a593Smuzhiyun void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data)
589*4882a593Smuzhiyun {
590*4882a593Smuzhiyun ep93xx_keypad_data = *data;
591*4882a593Smuzhiyun platform_device_register(&ep93xx_keypad_device);
592*4882a593Smuzhiyun }
593*4882a593Smuzhiyun
ep93xx_keypad_acquire_gpio(struct platform_device * pdev)594*4882a593Smuzhiyun int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)
595*4882a593Smuzhiyun {
596*4882a593Smuzhiyun int err;
597*4882a593Smuzhiyun int i;
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun for (i = 0; i < 8; i++) {
600*4882a593Smuzhiyun err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev));
601*4882a593Smuzhiyun if (err)
602*4882a593Smuzhiyun goto fail_gpio_c;
603*4882a593Smuzhiyun err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev));
604*4882a593Smuzhiyun if (err)
605*4882a593Smuzhiyun goto fail_gpio_d;
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun /* Enable the keypad controller; GPIO ports C and D used for keypad */
609*4882a593Smuzhiyun ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS |
610*4882a593Smuzhiyun EP93XX_SYSCON_DEVCFG_GONK);
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun return 0;
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun fail_gpio_d:
615*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_C(i));
616*4882a593Smuzhiyun fail_gpio_c:
617*4882a593Smuzhiyun for (--i; i >= 0; --i) {
618*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_C(i));
619*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_D(i));
620*4882a593Smuzhiyun }
621*4882a593Smuzhiyun return err;
622*4882a593Smuzhiyun }
623*4882a593Smuzhiyun EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio);
624*4882a593Smuzhiyun
ep93xx_keypad_release_gpio(struct platform_device * pdev)625*4882a593Smuzhiyun void ep93xx_keypad_release_gpio(struct platform_device *pdev)
626*4882a593Smuzhiyun {
627*4882a593Smuzhiyun int i;
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun for (i = 0; i < 8; i++) {
630*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_C(i));
631*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_D(i));
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun /* Disable the keypad controller; GPIO ports C and D used for GPIO */
635*4882a593Smuzhiyun ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
636*4882a593Smuzhiyun EP93XX_SYSCON_DEVCFG_GONK);
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun /*************************************************************************
641*4882a593Smuzhiyun * EP93xx I2S audio peripheral handling
642*4882a593Smuzhiyun *************************************************************************/
643*4882a593Smuzhiyun static struct resource ep93xx_i2s_resource[] = {
644*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100),
645*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_SAI),
646*4882a593Smuzhiyun };
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun static struct platform_device ep93xx_i2s_device = {
649*4882a593Smuzhiyun .name = "ep93xx-i2s",
650*4882a593Smuzhiyun .id = -1,
651*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_i2s_resource),
652*4882a593Smuzhiyun .resource = ep93xx_i2s_resource,
653*4882a593Smuzhiyun };
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun static struct platform_device ep93xx_pcm_device = {
656*4882a593Smuzhiyun .name = "ep93xx-pcm-audio",
657*4882a593Smuzhiyun .id = -1,
658*4882a593Smuzhiyun };
659*4882a593Smuzhiyun
ep93xx_register_i2s(void)660*4882a593Smuzhiyun void __init ep93xx_register_i2s(void)
661*4882a593Smuzhiyun {
662*4882a593Smuzhiyun platform_device_register(&ep93xx_i2s_device);
663*4882a593Smuzhiyun platform_device_register(&ep93xx_pcm_device);
664*4882a593Smuzhiyun }
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun #define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \
667*4882a593Smuzhiyun EP93XX_SYSCON_DEVCFG_I2SONAC97)
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun #define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
670*4882a593Smuzhiyun EP93XX_SYSCON_I2SCLKDIV_SPOL)
671*4882a593Smuzhiyun
ep93xx_i2s_acquire(void)672*4882a593Smuzhiyun int ep93xx_i2s_acquire(void)
673*4882a593Smuzhiyun {
674*4882a593Smuzhiyun unsigned val;
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97,
677*4882a593Smuzhiyun EP93XX_SYSCON_DEVCFG_I2S_MASK);
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun /*
680*4882a593Smuzhiyun * This is potentially racy with the clock api for i2s_mclk, sclk and
681*4882a593Smuzhiyun * lrclk. Since the i2s driver is the only user of those clocks we
682*4882a593Smuzhiyun * rely on it to prevent parallel use of this function and the
683*4882a593Smuzhiyun * clock api for the i2s clocks.
684*4882a593Smuzhiyun */
685*4882a593Smuzhiyun val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
686*4882a593Smuzhiyun val &= ~EP93XX_I2SCLKDIV_MASK;
687*4882a593Smuzhiyun val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
688*4882a593Smuzhiyun ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun return 0;
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun EXPORT_SYMBOL(ep93xx_i2s_acquire);
693*4882a593Smuzhiyun
ep93xx_i2s_release(void)694*4882a593Smuzhiyun void ep93xx_i2s_release(void)
695*4882a593Smuzhiyun {
696*4882a593Smuzhiyun ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
697*4882a593Smuzhiyun }
698*4882a593Smuzhiyun EXPORT_SYMBOL(ep93xx_i2s_release);
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun /*************************************************************************
701*4882a593Smuzhiyun * EP93xx AC97 audio peripheral handling
702*4882a593Smuzhiyun *************************************************************************/
703*4882a593Smuzhiyun static struct resource ep93xx_ac97_resources[] = {
704*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac),
705*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR),
706*4882a593Smuzhiyun };
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun static struct platform_device ep93xx_ac97_device = {
709*4882a593Smuzhiyun .name = "ep93xx-ac97",
710*4882a593Smuzhiyun .id = -1,
711*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_ac97_resources),
712*4882a593Smuzhiyun .resource = ep93xx_ac97_resources,
713*4882a593Smuzhiyun };
714*4882a593Smuzhiyun
ep93xx_register_ac97(void)715*4882a593Smuzhiyun void __init ep93xx_register_ac97(void)
716*4882a593Smuzhiyun {
717*4882a593Smuzhiyun /*
718*4882a593Smuzhiyun * Make sure that the AC97 pins are not used by I2S.
719*4882a593Smuzhiyun */
720*4882a593Smuzhiyun ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97);
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun platform_device_register(&ep93xx_ac97_device);
723*4882a593Smuzhiyun platform_device_register(&ep93xx_pcm_device);
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun /*************************************************************************
727*4882a593Smuzhiyun * EP93xx Watchdog
728*4882a593Smuzhiyun *************************************************************************/
729*4882a593Smuzhiyun static struct resource ep93xx_wdt_resources[] = {
730*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08),
731*4882a593Smuzhiyun };
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun static struct platform_device ep93xx_wdt_device = {
734*4882a593Smuzhiyun .name = "ep93xx-wdt",
735*4882a593Smuzhiyun .id = -1,
736*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_wdt_resources),
737*4882a593Smuzhiyun .resource = ep93xx_wdt_resources,
738*4882a593Smuzhiyun };
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun /*************************************************************************
741*4882a593Smuzhiyun * EP93xx IDE
742*4882a593Smuzhiyun *************************************************************************/
743*4882a593Smuzhiyun static struct resource ep93xx_ide_resources[] = {
744*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38),
745*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_EXT3),
746*4882a593Smuzhiyun };
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun static struct platform_device ep93xx_ide_device = {
749*4882a593Smuzhiyun .name = "ep93xx-ide",
750*4882a593Smuzhiyun .id = -1,
751*4882a593Smuzhiyun .dev = {
752*4882a593Smuzhiyun .dma_mask = &ep93xx_ide_device.dev.coherent_dma_mask,
753*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
754*4882a593Smuzhiyun },
755*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_ide_resources),
756*4882a593Smuzhiyun .resource = ep93xx_ide_resources,
757*4882a593Smuzhiyun };
758*4882a593Smuzhiyun
ep93xx_register_ide(void)759*4882a593Smuzhiyun void __init ep93xx_register_ide(void)
760*4882a593Smuzhiyun {
761*4882a593Smuzhiyun platform_device_register(&ep93xx_ide_device);
762*4882a593Smuzhiyun }
763*4882a593Smuzhiyun
ep93xx_ide_acquire_gpio(struct platform_device * pdev)764*4882a593Smuzhiyun int ep93xx_ide_acquire_gpio(struct platform_device *pdev)
765*4882a593Smuzhiyun {
766*4882a593Smuzhiyun int err;
767*4882a593Smuzhiyun int i;
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun err = gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev));
770*4882a593Smuzhiyun if (err)
771*4882a593Smuzhiyun return err;
772*4882a593Smuzhiyun err = gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev));
773*4882a593Smuzhiyun if (err)
774*4882a593Smuzhiyun goto fail_egpio15;
775*4882a593Smuzhiyun for (i = 2; i < 8; i++) {
776*4882a593Smuzhiyun err = gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev));
777*4882a593Smuzhiyun if (err)
778*4882a593Smuzhiyun goto fail_gpio_e;
779*4882a593Smuzhiyun }
780*4882a593Smuzhiyun for (i = 4; i < 8; i++) {
781*4882a593Smuzhiyun err = gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev));
782*4882a593Smuzhiyun if (err)
783*4882a593Smuzhiyun goto fail_gpio_g;
784*4882a593Smuzhiyun }
785*4882a593Smuzhiyun for (i = 0; i < 8; i++) {
786*4882a593Smuzhiyun err = gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev));
787*4882a593Smuzhiyun if (err)
788*4882a593Smuzhiyun goto fail_gpio_h;
789*4882a593Smuzhiyun }
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun /* GPIO ports E[7:2], G[7:4] and H used by IDE */
792*4882a593Smuzhiyun ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
793*4882a593Smuzhiyun EP93XX_SYSCON_DEVCFG_GONIDE |
794*4882a593Smuzhiyun EP93XX_SYSCON_DEVCFG_HONIDE);
795*4882a593Smuzhiyun return 0;
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun fail_gpio_h:
798*4882a593Smuzhiyun for (--i; i >= 0; --i)
799*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_H(i));
800*4882a593Smuzhiyun i = 8;
801*4882a593Smuzhiyun fail_gpio_g:
802*4882a593Smuzhiyun for (--i; i >= 4; --i)
803*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_G(i));
804*4882a593Smuzhiyun i = 8;
805*4882a593Smuzhiyun fail_gpio_e:
806*4882a593Smuzhiyun for (--i; i >= 2; --i)
807*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_E(i));
808*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_EGPIO15);
809*4882a593Smuzhiyun fail_egpio15:
810*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_EGPIO2);
811*4882a593Smuzhiyun return err;
812*4882a593Smuzhiyun }
813*4882a593Smuzhiyun EXPORT_SYMBOL(ep93xx_ide_acquire_gpio);
814*4882a593Smuzhiyun
ep93xx_ide_release_gpio(struct platform_device * pdev)815*4882a593Smuzhiyun void ep93xx_ide_release_gpio(struct platform_device *pdev)
816*4882a593Smuzhiyun {
817*4882a593Smuzhiyun int i;
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun for (i = 2; i < 8; i++)
820*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_E(i));
821*4882a593Smuzhiyun for (i = 4; i < 8; i++)
822*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_G(i));
823*4882a593Smuzhiyun for (i = 0; i < 8; i++)
824*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_H(i));
825*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_EGPIO15);
826*4882a593Smuzhiyun gpio_free(EP93XX_GPIO_LINE_EGPIO2);
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun /* GPIO ports E[7:2], G[7:4] and H used by GPIO */
830*4882a593Smuzhiyun ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
831*4882a593Smuzhiyun EP93XX_SYSCON_DEVCFG_GONIDE |
832*4882a593Smuzhiyun EP93XX_SYSCON_DEVCFG_HONIDE);
833*4882a593Smuzhiyun }
834*4882a593Smuzhiyun EXPORT_SYMBOL(ep93xx_ide_release_gpio);
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun /*************************************************************************
837*4882a593Smuzhiyun * EP93xx ADC
838*4882a593Smuzhiyun *************************************************************************/
839*4882a593Smuzhiyun static struct resource ep93xx_adc_resources[] = {
840*4882a593Smuzhiyun DEFINE_RES_MEM(EP93XX_ADC_PHYS_BASE, 0x28),
841*4882a593Smuzhiyun DEFINE_RES_IRQ(IRQ_EP93XX_TOUCH),
842*4882a593Smuzhiyun };
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun static struct platform_device ep93xx_adc_device = {
845*4882a593Smuzhiyun .name = "ep93xx-adc",
846*4882a593Smuzhiyun .id = -1,
847*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(ep93xx_adc_resources),
848*4882a593Smuzhiyun .resource = ep93xx_adc_resources,
849*4882a593Smuzhiyun };
850*4882a593Smuzhiyun
ep93xx_register_adc(void)851*4882a593Smuzhiyun void __init ep93xx_register_adc(void)
852*4882a593Smuzhiyun {
853*4882a593Smuzhiyun /* Power up ADC, deactivate Touch Screen Controller */
854*4882a593Smuzhiyun ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_TIN,
855*4882a593Smuzhiyun EP93XX_SYSCON_DEVCFG_ADCPD);
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun platform_device_register(&ep93xx_adc_device);
858*4882a593Smuzhiyun }
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun /*************************************************************************
861*4882a593Smuzhiyun * EP93xx Security peripheral
862*4882a593Smuzhiyun *************************************************************************/
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun /*
865*4882a593Smuzhiyun * The Maverick Key is 256 bits of micro fuses blown at the factory during
866*4882a593Smuzhiyun * manufacturing to uniquely identify a part.
867*4882a593Smuzhiyun *
868*4882a593Smuzhiyun * See: http://arm.cirrus.com/forum/viewtopic.php?t=486&highlight=maverick+key
869*4882a593Smuzhiyun */
870*4882a593Smuzhiyun #define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x))
871*4882a593Smuzhiyun #define EP93XX_SECURITY_SECFLG EP93XX_SECURITY_REG(0x2400)
872*4882a593Smuzhiyun #define EP93XX_SECURITY_FUSEFLG EP93XX_SECURITY_REG(0x2410)
873*4882a593Smuzhiyun #define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440)
874*4882a593Smuzhiyun #define EP93XX_SECURITY_UNIQCHK EP93XX_SECURITY_REG(0x2450)
875*4882a593Smuzhiyun #define EP93XX_SECURITY_UNIQVAL EP93XX_SECURITY_REG(0x2460)
876*4882a593Smuzhiyun #define EP93XX_SECURITY_SECID1 EP93XX_SECURITY_REG(0x2500)
877*4882a593Smuzhiyun #define EP93XX_SECURITY_SECID2 EP93XX_SECURITY_REG(0x2504)
878*4882a593Smuzhiyun #define EP93XX_SECURITY_SECCHK1 EP93XX_SECURITY_REG(0x2520)
879*4882a593Smuzhiyun #define EP93XX_SECURITY_SECCHK2 EP93XX_SECURITY_REG(0x2524)
880*4882a593Smuzhiyun #define EP93XX_SECURITY_UNIQID2 EP93XX_SECURITY_REG(0x2700)
881*4882a593Smuzhiyun #define EP93XX_SECURITY_UNIQID3 EP93XX_SECURITY_REG(0x2704)
882*4882a593Smuzhiyun #define EP93XX_SECURITY_UNIQID4 EP93XX_SECURITY_REG(0x2708)
883*4882a593Smuzhiyun #define EP93XX_SECURITY_UNIQID5 EP93XX_SECURITY_REG(0x270c)
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun static char ep93xx_soc_id[33];
886*4882a593Smuzhiyun
ep93xx_get_soc_id(void)887*4882a593Smuzhiyun static const char __init *ep93xx_get_soc_id(void)
888*4882a593Smuzhiyun {
889*4882a593Smuzhiyun unsigned int id, id2, id3, id4, id5;
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun if (__raw_readl(EP93XX_SECURITY_UNIQVAL) != 1)
892*4882a593Smuzhiyun return "bad Hamming code";
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun id = __raw_readl(EP93XX_SECURITY_UNIQID);
895*4882a593Smuzhiyun id2 = __raw_readl(EP93XX_SECURITY_UNIQID2);
896*4882a593Smuzhiyun id3 = __raw_readl(EP93XX_SECURITY_UNIQID3);
897*4882a593Smuzhiyun id4 = __raw_readl(EP93XX_SECURITY_UNIQID4);
898*4882a593Smuzhiyun id5 = __raw_readl(EP93XX_SECURITY_UNIQID5);
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun if (id != id2)
901*4882a593Smuzhiyun return "invalid";
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun /* Toss the unique ID into the entropy pool */
904*4882a593Smuzhiyun add_device_randomness(&id2, 4);
905*4882a593Smuzhiyun add_device_randomness(&id3, 4);
906*4882a593Smuzhiyun add_device_randomness(&id4, 4);
907*4882a593Smuzhiyun add_device_randomness(&id5, 4);
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id),
910*4882a593Smuzhiyun "%08x%08x%08x%08x", id2, id3, id4, id5);
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun return ep93xx_soc_id;
913*4882a593Smuzhiyun }
914*4882a593Smuzhiyun
ep93xx_get_soc_rev(void)915*4882a593Smuzhiyun static const char __init *ep93xx_get_soc_rev(void)
916*4882a593Smuzhiyun {
917*4882a593Smuzhiyun int rev = ep93xx_chip_revision();
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun switch (rev) {
920*4882a593Smuzhiyun case EP93XX_CHIP_REV_D0:
921*4882a593Smuzhiyun return "D0";
922*4882a593Smuzhiyun case EP93XX_CHIP_REV_D1:
923*4882a593Smuzhiyun return "D1";
924*4882a593Smuzhiyun case EP93XX_CHIP_REV_E0:
925*4882a593Smuzhiyun return "E0";
926*4882a593Smuzhiyun case EP93XX_CHIP_REV_E1:
927*4882a593Smuzhiyun return "E1";
928*4882a593Smuzhiyun case EP93XX_CHIP_REV_E2:
929*4882a593Smuzhiyun return "E2";
930*4882a593Smuzhiyun default:
931*4882a593Smuzhiyun return "unknown";
932*4882a593Smuzhiyun }
933*4882a593Smuzhiyun }
934*4882a593Smuzhiyun
ep93xx_get_machine_name(void)935*4882a593Smuzhiyun static const char __init *ep93xx_get_machine_name(void)
936*4882a593Smuzhiyun {
937*4882a593Smuzhiyun return kasprintf(GFP_KERNEL,"%s", machine_desc->name);
938*4882a593Smuzhiyun }
939*4882a593Smuzhiyun
ep93xx_init_soc(void)940*4882a593Smuzhiyun static struct device __init *ep93xx_init_soc(void)
941*4882a593Smuzhiyun {
942*4882a593Smuzhiyun struct soc_device_attribute *soc_dev_attr;
943*4882a593Smuzhiyun struct soc_device *soc_dev;
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
946*4882a593Smuzhiyun if (!soc_dev_attr)
947*4882a593Smuzhiyun return NULL;
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun soc_dev_attr->machine = ep93xx_get_machine_name();
950*4882a593Smuzhiyun soc_dev_attr->family = "Cirrus Logic EP93xx";
951*4882a593Smuzhiyun soc_dev_attr->revision = ep93xx_get_soc_rev();
952*4882a593Smuzhiyun soc_dev_attr->soc_id = ep93xx_get_soc_id();
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun soc_dev = soc_device_register(soc_dev_attr);
955*4882a593Smuzhiyun if (IS_ERR(soc_dev)) {
956*4882a593Smuzhiyun kfree(soc_dev_attr->machine);
957*4882a593Smuzhiyun kfree(soc_dev_attr);
958*4882a593Smuzhiyun return NULL;
959*4882a593Smuzhiyun }
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun return soc_device_to_device(soc_dev);
962*4882a593Smuzhiyun }
963*4882a593Smuzhiyun
ep93xx_init_devices(void)964*4882a593Smuzhiyun struct device __init *ep93xx_init_devices(void)
965*4882a593Smuzhiyun {
966*4882a593Smuzhiyun struct device *parent;
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun /* Disallow access to MaverickCrunch initially */
969*4882a593Smuzhiyun ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun /* Default all ports to GPIO */
972*4882a593Smuzhiyun ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
973*4882a593Smuzhiyun EP93XX_SYSCON_DEVCFG_GONK |
974*4882a593Smuzhiyun EP93XX_SYSCON_DEVCFG_EONIDE |
975*4882a593Smuzhiyun EP93XX_SYSCON_DEVCFG_GONIDE |
976*4882a593Smuzhiyun EP93XX_SYSCON_DEVCFG_HONIDE);
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun parent = ep93xx_init_soc();
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun /* Get the GPIO working early, other devices need it */
981*4882a593Smuzhiyun platform_device_register(&ep93xx_gpio_device);
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun amba_device_register(&uart1_device, &iomem_resource);
984*4882a593Smuzhiyun amba_device_register(&uart2_device, &iomem_resource);
985*4882a593Smuzhiyun amba_device_register(&uart3_device, &iomem_resource);
986*4882a593Smuzhiyun
987*4882a593Smuzhiyun platform_device_register(&ep93xx_rtc_device);
988*4882a593Smuzhiyun platform_device_register(&ep93xx_ohci_device);
989*4882a593Smuzhiyun platform_device_register(&ep93xx_wdt_device);
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun gpio_led_register_device(-1, &ep93xx_led_data);
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun return parent;
994*4882a593Smuzhiyun }
995*4882a593Smuzhiyun
ep93xx_restart(enum reboot_mode mode,const char * cmd)996*4882a593Smuzhiyun void ep93xx_restart(enum reboot_mode mode, const char *cmd)
997*4882a593Smuzhiyun {
998*4882a593Smuzhiyun /*
999*4882a593Smuzhiyun * Set then clear the SWRST bit to initiate a software reset
1000*4882a593Smuzhiyun */
1001*4882a593Smuzhiyun ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
1002*4882a593Smuzhiyun ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun while (1)
1005*4882a593Smuzhiyun ;
1006*4882a593Smuzhiyun }
1007*4882a593Smuzhiyun
ep93xx_init_late(void)1008*4882a593Smuzhiyun void __init ep93xx_init_late(void)
1009*4882a593Smuzhiyun {
1010*4882a593Smuzhiyun crunch_init();
1011*4882a593Smuzhiyun }
1012