1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * IRQ definitions for Marvell Dove 88AP510 SoC 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 5*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 6*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_IRQS_H 10*4882a593Smuzhiyun #define __ASM_ARCH_IRQS_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Dove Low Interrupt Controller 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define IRQ_DOVE_BRIDGE (1 + 0) 16*4882a593Smuzhiyun #define IRQ_DOVE_H2C (1 + 1) 17*4882a593Smuzhiyun #define IRQ_DOVE_C2H (1 + 2) 18*4882a593Smuzhiyun #define IRQ_DOVE_NAND (1 + 3) 19*4882a593Smuzhiyun #define IRQ_DOVE_PDMA (1 + 4) 20*4882a593Smuzhiyun #define IRQ_DOVE_SPI1 (1 + 5) 21*4882a593Smuzhiyun #define IRQ_DOVE_SPI0 (1 + 6) 22*4882a593Smuzhiyun #define IRQ_DOVE_UART_0 (1 + 7) 23*4882a593Smuzhiyun #define IRQ_DOVE_UART_1 (1 + 8) 24*4882a593Smuzhiyun #define IRQ_DOVE_UART_2 (1 + 9) 25*4882a593Smuzhiyun #define IRQ_DOVE_UART_3 (1 + 10) 26*4882a593Smuzhiyun #define IRQ_DOVE_I2C (1 + 11) 27*4882a593Smuzhiyun #define IRQ_DOVE_GPIO_0_7 (1 + 12) 28*4882a593Smuzhiyun #define IRQ_DOVE_GPIO_8_15 (1 + 13) 29*4882a593Smuzhiyun #define IRQ_DOVE_GPIO_16_23 (1 + 14) 30*4882a593Smuzhiyun #define IRQ_DOVE_PCIE0_ERR (1 + 15) 31*4882a593Smuzhiyun #define IRQ_DOVE_PCIE0 (1 + 16) 32*4882a593Smuzhiyun #define IRQ_DOVE_PCIE1_ERR (1 + 17) 33*4882a593Smuzhiyun #define IRQ_DOVE_PCIE1 (1 + 18) 34*4882a593Smuzhiyun #define IRQ_DOVE_I2S0 (1 + 19) 35*4882a593Smuzhiyun #define IRQ_DOVE_I2S0_ERR (1 + 20) 36*4882a593Smuzhiyun #define IRQ_DOVE_I2S1 (1 + 21) 37*4882a593Smuzhiyun #define IRQ_DOVE_I2S1_ERR (1 + 22) 38*4882a593Smuzhiyun #define IRQ_DOVE_USB_ERR (1 + 23) 39*4882a593Smuzhiyun #define IRQ_DOVE_USB0 (1 + 24) 40*4882a593Smuzhiyun #define IRQ_DOVE_USB1 (1 + 25) 41*4882a593Smuzhiyun #define IRQ_DOVE_GE00_RX (1 + 26) 42*4882a593Smuzhiyun #define IRQ_DOVE_GE00_TX (1 + 27) 43*4882a593Smuzhiyun #define IRQ_DOVE_GE00_MISC (1 + 28) 44*4882a593Smuzhiyun #define IRQ_DOVE_GE00_SUM (1 + 29) 45*4882a593Smuzhiyun #define IRQ_DOVE_GE00_ERR (1 + 30) 46*4882a593Smuzhiyun #define IRQ_DOVE_CRYPTO (1 + 31) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * Dove High Interrupt Controller 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define IRQ_DOVE_AC97 (1 + 32) 52*4882a593Smuzhiyun #define IRQ_DOVE_PMU (1 + 33) 53*4882a593Smuzhiyun #define IRQ_DOVE_CAM (1 + 34) 54*4882a593Smuzhiyun #define IRQ_DOVE_SDIO0 (1 + 35) 55*4882a593Smuzhiyun #define IRQ_DOVE_SDIO1 (1 + 36) 56*4882a593Smuzhiyun #define IRQ_DOVE_SDIO0_WAKEUP (1 + 37) 57*4882a593Smuzhiyun #define IRQ_DOVE_SDIO1_WAKEUP (1 + 38) 58*4882a593Smuzhiyun #define IRQ_DOVE_XOR_00 (1 + 39) 59*4882a593Smuzhiyun #define IRQ_DOVE_XOR_01 (1 + 40) 60*4882a593Smuzhiyun #define IRQ_DOVE_XOR0_ERR (1 + 41) 61*4882a593Smuzhiyun #define IRQ_DOVE_XOR_10 (1 + 42) 62*4882a593Smuzhiyun #define IRQ_DOVE_XOR_11 (1 + 43) 63*4882a593Smuzhiyun #define IRQ_DOVE_XOR1_ERR (1 + 44) 64*4882a593Smuzhiyun #define IRQ_DOVE_LCD_DCON (1 + 45) 65*4882a593Smuzhiyun #define IRQ_DOVE_LCD1 (1 + 46) 66*4882a593Smuzhiyun #define IRQ_DOVE_LCD0 (1 + 47) 67*4882a593Smuzhiyun #define IRQ_DOVE_GPU (1 + 48) 68*4882a593Smuzhiyun #define IRQ_DOVE_PERFORM_MNTR (1 + 49) 69*4882a593Smuzhiyun #define IRQ_DOVE_VPRO_DMA1 (1 + 51) 70*4882a593Smuzhiyun #define IRQ_DOVE_SSP_TIMER (1 + 54) 71*4882a593Smuzhiyun #define IRQ_DOVE_SSP (1 + 55) 72*4882a593Smuzhiyun #define IRQ_DOVE_MC_L2_ERR (1 + 56) 73*4882a593Smuzhiyun #define IRQ_DOVE_CRYPTO_ERR (1 + 59) 74*4882a593Smuzhiyun #define IRQ_DOVE_GPIO_24_31 (1 + 60) 75*4882a593Smuzhiyun #define IRQ_DOVE_HIGH_GPIO (1 + 61) 76*4882a593Smuzhiyun #define IRQ_DOVE_SATA (1 + 62) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * DOVE General Purpose Pins 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun #define IRQ_DOVE_GPIO_START 65 82*4882a593Smuzhiyun #define NR_GPIO_IRQS 64 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * PMU interrupts 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun #define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS) 88*4882a593Smuzhiyun #define NR_PMU_IRQS 7 89*4882a593Smuzhiyun #define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define DOVE_NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #endif 95