1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/arm/mach-dove/irq.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Dove IRQ handling.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
8*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <asm/exception.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <plat/irq.h>
16*4882a593Smuzhiyun #include <plat/orion-gpio.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "pm.h"
19*4882a593Smuzhiyun #include "bridge-regs.h"
20*4882a593Smuzhiyun #include "common.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static int __initdata gpio0_irqs[4] = {
23*4882a593Smuzhiyun IRQ_DOVE_GPIO_0_7,
24*4882a593Smuzhiyun IRQ_DOVE_GPIO_8_15,
25*4882a593Smuzhiyun IRQ_DOVE_GPIO_16_23,
26*4882a593Smuzhiyun IRQ_DOVE_GPIO_24_31,
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static int __initdata gpio1_irqs[4] = {
30*4882a593Smuzhiyun IRQ_DOVE_HIGH_GPIO,
31*4882a593Smuzhiyun 0,
32*4882a593Smuzhiyun 0,
33*4882a593Smuzhiyun 0,
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun static int __initdata gpio2_irqs[4] = {
37*4882a593Smuzhiyun 0,
38*4882a593Smuzhiyun 0,
39*4882a593Smuzhiyun 0,
40*4882a593Smuzhiyun 0,
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static void __iomem *dove_irq_base = IRQ_VIRT_BASE;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static asmlinkage void
dove_legacy_handle_irq(struct pt_regs * regs)46*4882a593Smuzhiyun __exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun u32 stat;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
51*4882a593Smuzhiyun stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
52*4882a593Smuzhiyun if (stat) {
53*4882a593Smuzhiyun unsigned int hwirq = 1 + __fls(stat);
54*4882a593Smuzhiyun handle_IRQ(hwirq, regs);
55*4882a593Smuzhiyun return;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
58*4882a593Smuzhiyun stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
59*4882a593Smuzhiyun if (stat) {
60*4882a593Smuzhiyun unsigned int hwirq = 33 + __fls(stat);
61*4882a593Smuzhiyun handle_IRQ(hwirq, regs);
62*4882a593Smuzhiyun return;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
dove_init_irq(void)66*4882a593Smuzhiyun void __init dove_init_irq(void)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
69*4882a593Smuzhiyun orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun set_handle_irq(dove_legacy_handle_irq);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun * Initialize gpiolib for GPIOs 0-71.
75*4882a593Smuzhiyun */
76*4882a593Smuzhiyun orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
77*4882a593Smuzhiyun IRQ_DOVE_GPIO_START, gpio0_irqs);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
80*4882a593Smuzhiyun IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
83*4882a593Smuzhiyun IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
84*4882a593Smuzhiyun }
85