1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Generic definitions for Marvell Dove 88AP510 SoC 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 5*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 6*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_DOVE_H 10*4882a593Smuzhiyun #define __ASM_ARCH_DOVE_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "irqs.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Marvell Dove address maps. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * phys virt size 18*4882a593Smuzhiyun * c8000000 fdb00000 1M Cryptographic SRAM 19*4882a593Smuzhiyun * e0000000 @runtime 128M PCIe-0 Memory space 20*4882a593Smuzhiyun * e8000000 @runtime 128M PCIe-1 Memory space 21*4882a593Smuzhiyun * f1000000 fec00000 1M on-chip south-bridge registers 22*4882a593Smuzhiyun * f1800000 fe400000 8M on-chip north-bridge registers 23*4882a593Smuzhiyun * f2000000 fee00000 1M PCIe-0 I/O space 24*4882a593Smuzhiyun * f2100000 fef00000 1M PCIe-1 I/O space 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define DOVE_CESA_PHYS_BASE 0xc8000000 28*4882a593Smuzhiyun #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000) 29*4882a593Smuzhiyun #define DOVE_CESA_SIZE SZ_1M 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 32*4882a593Smuzhiyun #define DOVE_PCIE0_MEM_SIZE SZ_128M 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000 35*4882a593Smuzhiyun #define DOVE_PCIE1_MEM_SIZE SZ_128M 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define DOVE_BOOTROM_PHYS_BASE 0xf8000000 38*4882a593Smuzhiyun #define DOVE_BOOTROM_SIZE SZ_128M 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 41*4882a593Smuzhiyun #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000) 42*4882a593Smuzhiyun #define DOVE_SCRATCHPAD_SIZE SZ_1M 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define DOVE_SB_REGS_PHYS_BASE 0xf1000000 45*4882a593Smuzhiyun #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000) 46*4882a593Smuzhiyun #define DOVE_SB_REGS_SIZE SZ_1M 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define DOVE_NB_REGS_PHYS_BASE 0xf1800000 49*4882a593Smuzhiyun #define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000) 50*4882a593Smuzhiyun #define DOVE_NB_REGS_SIZE SZ_8M 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 53*4882a593Smuzhiyun #define DOVE_PCIE0_IO_BUS_BASE 0x00000000 54*4882a593Smuzhiyun #define DOVE_PCIE0_IO_SIZE SZ_64K 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 57*4882a593Smuzhiyun #define DOVE_PCIE1_IO_BUS_BASE 0x00010000 58*4882a593Smuzhiyun #define DOVE_PCIE1_IO_SIZE SZ_64K 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * Dove Core Registers Map 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* SPI, I2C, UART */ 65*4882a593Smuzhiyun #define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000) 66*4882a593Smuzhiyun #define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000) 67*4882a593Smuzhiyun #define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000) 68*4882a593Smuzhiyun #define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100) 69*4882a593Smuzhiyun #define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100) 70*4882a593Smuzhiyun #define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200) 71*4882a593Smuzhiyun #define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200) 72*4882a593Smuzhiyun #define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300) 73*4882a593Smuzhiyun #define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300) 74*4882a593Smuzhiyun #define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600) 75*4882a593Smuzhiyun #define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* North-South Bridge */ 78*4882a593Smuzhiyun #define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) 79*4882a593Smuzhiyun #define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000) 80*4882a593Smuzhiyun #define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE) 81*4882a593Smuzhiyun #define BRIDGE_WINS_SZ (0x80) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* Cryptographic Engine */ 84*4882a593Smuzhiyun #define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* PCIe 0 */ 87*4882a593Smuzhiyun #define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* USB */ 90*4882a593Smuzhiyun #define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000) 91*4882a593Smuzhiyun #define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* XOR 0 Engine */ 94*4882a593Smuzhiyun #define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800) 95*4882a593Smuzhiyun #define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800) 96*4882a593Smuzhiyun #define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00) 97*4882a593Smuzhiyun #define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* XOR 1 Engine */ 100*4882a593Smuzhiyun #define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900) 101*4882a593Smuzhiyun #define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900) 102*4882a593Smuzhiyun #define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00) 103*4882a593Smuzhiyun #define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* Gigabit Ethernet */ 106*4882a593Smuzhiyun #define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* PCIe 1 */ 109*4882a593Smuzhiyun #define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* CAFE */ 112*4882a593Smuzhiyun #define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000) 113*4882a593Smuzhiyun #define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000) 114*4882a593Smuzhiyun #define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000) 115*4882a593Smuzhiyun #define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* SATA */ 118*4882a593Smuzhiyun #define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* I2S/SPDIF */ 121*4882a593Smuzhiyun #define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000) 122*4882a593Smuzhiyun #define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* NAND Flash Controller */ 125*4882a593Smuzhiyun #define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* MPP, GPIO, Reset Sampling */ 128*4882a593Smuzhiyun #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) 129*4882a593Smuzhiyun #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 130*4882a593Smuzhiyun #define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014) 131*4882a593Smuzhiyun #define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018) 132*4882a593Smuzhiyun #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) 133*4882a593Smuzhiyun #define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420) 134*4882a593Smuzhiyun #define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400) 135*4882a593Smuzhiyun #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) 136*4882a593Smuzhiyun #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) 137*4882a593Smuzhiyun #define DOVE_NAND_GPIO_EN (1 << 0) 138*4882a593Smuzhiyun #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) 139*4882a593Smuzhiyun #define DOVE_SPI_GPIO_SEL (1 << 5) 140*4882a593Smuzhiyun #define DOVE_UART1_GPIO_SEL (1 << 4) 141*4882a593Smuzhiyun #define DOVE_AU1_GPIO_SEL (1 << 3) 142*4882a593Smuzhiyun #define DOVE_CAM_GPIO_SEL (1 << 2) 143*4882a593Smuzhiyun #define DOVE_SD1_GPIO_SEL (1 << 1) 144*4882a593Smuzhiyun #define DOVE_SD0_GPIO_SEL (1 << 0) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* Power Management */ 147*4882a593Smuzhiyun #define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000) 148*4882a593Smuzhiyun #define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c) 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* Real Time Clock */ 151*4882a593Smuzhiyun #define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500) 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* AC97 */ 154*4882a593Smuzhiyun #define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000) 155*4882a593Smuzhiyun #define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000) 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /* Peripheral DMA */ 158*4882a593Smuzhiyun #define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000) 159*4882a593Smuzhiyun #define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000) 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 162*4882a593Smuzhiyun #define DOVE_TWSI_ENABLE_OPTION1 (1 << 7) 163*4882a593Smuzhiyun #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) 164*4882a593Smuzhiyun #define DOVE_TWSI_ENABLE_OPTION2 (1 << 20) 165*4882a593Smuzhiyun #define DOVE_TWSI_ENABLE_OPTION3 (1 << 21) 166*4882a593Smuzhiyun #define DOVE_TWSI_OPTION3_GPIO (1 << 22) 167*4882a593Smuzhiyun #define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000) 168*4882a593Smuzhiyun #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) 169*4882a593Smuzhiyun #define DOVE_SSP_ON_AU1 (1 << 0) 170*4882a593Smuzhiyun #define DOVE_SSP_CLOCK_ENABLE (1 << 1) 171*4882a593Smuzhiyun #define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) 172*4882a593Smuzhiyun /* Memory Controller */ 173*4882a593Smuzhiyun #define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000) 174*4882a593Smuzhiyun #define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100) 175*4882a593Smuzhiyun #define DOVE_MC_WINS_SZ (0x8) 176*4882a593Smuzhiyun #define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* LCD Controller */ 179*4882a593Smuzhiyun #define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) 180*4882a593Smuzhiyun #define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000) 181*4882a593Smuzhiyun #define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) 182*4882a593Smuzhiyun #define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000) 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun /* Graphic Engine */ 185*4882a593Smuzhiyun #define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000) 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* Video Engine */ 188*4882a593Smuzhiyun #define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000) 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #endif 191