1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Mbus-L to Mbus Bridge Registers 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 5*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 6*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_BRIDGE_REGS_H 10*4882a593Smuzhiyun #define __ASM_ARCH_BRIDGE_REGS_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "dove.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) 17*4882a593Smuzhiyun #define CPU_CTRL_PCIE0_LINK 0x00000001 18*4882a593Smuzhiyun #define CPU_RESET 0x00000002 19*4882a593Smuzhiyun #define CPU_CTRL_PCIE1_LINK 0x00000008 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) 22*4882a593Smuzhiyun #define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) 23*4882a593Smuzhiyun #define SOFT_RESET_OUT_EN 0x00000004 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) 26*4882a593Smuzhiyun #define SOFT_RESET 0x00000001 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) 29*4882a593Smuzhiyun #define BRIDGE_INT_TIMER1_CLR (~0x0004) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) 32*4882a593Smuzhiyun #define IRQ_CAUSE_LOW_OFF 0x0000 33*4882a593Smuzhiyun #define IRQ_MASK_LOW_OFF 0x0004 34*4882a593Smuzhiyun #define FIQ_MASK_LOW_OFF 0x0008 35*4882a593Smuzhiyun #define ENDPOINT_MASK_LOW_OFF 0x000c 36*4882a593Smuzhiyun #define IRQ_CAUSE_HIGH_OFF 0x0010 37*4882a593Smuzhiyun #define IRQ_MASK_HIGH_OFF 0x0014 38*4882a593Smuzhiyun #define FIQ_MASK_HIGH_OFF 0x0018 39*4882a593Smuzhiyun #define ENDPOINT_MASK_HIGH_OFF 0x001c 40*4882a593Smuzhiyun #define PCIE_INTERRUPT_MASK_OFF 0x0020 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF) 43*4882a593Smuzhiyun #define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF) 44*4882a593Smuzhiyun #define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF) 45*4882a593Smuzhiyun #define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF) 46*4882a593Smuzhiyun #define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF) 47*4882a593Smuzhiyun #define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) 48*4882a593Smuzhiyun #define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) 53*4882a593Smuzhiyun #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #endif 56