1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * mach-davinci/sram.c - DaVinci simple SRAM allocator
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2009 David Brownell
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/genalloc.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <mach/common.h>
13*4882a593Smuzhiyun #include "sram.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static struct gen_pool *sram_pool;
16*4882a593Smuzhiyun
sram_get_gen_pool(void)17*4882a593Smuzhiyun struct gen_pool *sram_get_gen_pool(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun return sram_pool;
20*4882a593Smuzhiyun }
21*4882a593Smuzhiyun
sram_alloc(size_t len,dma_addr_t * dma)22*4882a593Smuzhiyun void *sram_alloc(size_t len, dma_addr_t *dma)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun dma_addr_t dma_base = davinci_soc_info.sram_dma;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun if (dma)
27*4882a593Smuzhiyun *dma = 0;
28*4882a593Smuzhiyun if (!sram_pool || (dma && !dma_base))
29*4882a593Smuzhiyun return NULL;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun return gen_pool_dma_alloc(sram_pool, len, dma);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun EXPORT_SYMBOL(sram_alloc);
35*4882a593Smuzhiyun
sram_free(void * addr,size_t len)36*4882a593Smuzhiyun void sram_free(void *addr, size_t len)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun gen_pool_free(sram_pool, (unsigned long) addr, len);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun EXPORT_SYMBOL(sram_free);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /*
44*4882a593Smuzhiyun * REVISIT This supports CPU and DMA access to/from SRAM, but it
45*4882a593Smuzhiyun * doesn't (yet?) support some other notable uses of SRAM: as TCM
46*4882a593Smuzhiyun * for data and/or instructions; and holding code needed to enter
47*4882a593Smuzhiyun * and exit suspend states (while DRAM can't be used).
48*4882a593Smuzhiyun */
sram_init(void)49*4882a593Smuzhiyun static int __init sram_init(void)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun phys_addr_t phys = davinci_soc_info.sram_dma;
52*4882a593Smuzhiyun unsigned len = davinci_soc_info.sram_len;
53*4882a593Smuzhiyun int status = 0;
54*4882a593Smuzhiyun void __iomem *addr;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (len) {
57*4882a593Smuzhiyun len = min_t(unsigned, len, SRAM_SIZE);
58*4882a593Smuzhiyun sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1);
59*4882a593Smuzhiyun if (!sram_pool)
60*4882a593Smuzhiyun status = -ENOMEM;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun if (sram_pool) {
64*4882a593Smuzhiyun addr = ioremap(phys, len);
65*4882a593Smuzhiyun if (!addr)
66*4882a593Smuzhiyun return -ENOMEM;
67*4882a593Smuzhiyun status = gen_pool_add_virt(sram_pool, (unsigned long) addr,
68*4882a593Smuzhiyun phys, len, -1);
69*4882a593Smuzhiyun if (status < 0)
70*4882a593Smuzhiyun iounmap(addr);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun WARN_ON(status < 0);
74*4882a593Smuzhiyun return status;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun core_initcall(sram_init);
77*4882a593Smuzhiyun
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