1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * TI DaVinci serial driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2006 Texas Instruments.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/serial_8250.h>
11*4882a593Smuzhiyun #include <linux/serial_reg.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/clk.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <mach/serial.h>
18*4882a593Smuzhiyun #include <mach/cputype.h>
19*4882a593Smuzhiyun
serial_write_reg(struct plat_serial8250_port * p,int offset,int value)20*4882a593Smuzhiyun static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
21*4882a593Smuzhiyun int value)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun offset <<= p->regshift;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun __raw_writel(value, p->membase + offset);
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
davinci_serial_reset(struct plat_serial8250_port * p)30*4882a593Smuzhiyun static void __init davinci_serial_reset(struct plat_serial8250_port *p)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun unsigned int pwremu = 0;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun serial_write_reg(p, UART_IER, 0); /* disable all interrupts */
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
37*4882a593Smuzhiyun serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
38*4882a593Smuzhiyun mdelay(10);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun pwremu |= (0x3 << 13);
41*4882a593Smuzhiyun pwremu |= 0x1;
42*4882a593Smuzhiyun serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun if (cpu_is_davinci_dm646x())
45*4882a593Smuzhiyun serial_write_reg(p, UART_DM646X_SCR,
46*4882a593Smuzhiyun UART_DM646X_SCR_TX_WATERMARK);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
davinci_serial_init(struct platform_device * serial_dev)49*4882a593Smuzhiyun int __init davinci_serial_init(struct platform_device *serial_dev)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun int i, ret = 0;
52*4882a593Smuzhiyun struct device *dev;
53*4882a593Smuzhiyun struct plat_serial8250_port *p;
54*4882a593Smuzhiyun struct clk *clk;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun * Make sure the serial ports are muxed on at this point.
58*4882a593Smuzhiyun * You have to mux them off in device drivers later on if not needed.
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun for (i = 0; serial_dev[i].dev.platform_data != NULL; i++) {
61*4882a593Smuzhiyun dev = &serial_dev[i].dev;
62*4882a593Smuzhiyun p = dev->platform_data;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun ret = platform_device_register(&serial_dev[i]);
65*4882a593Smuzhiyun if (ret)
66*4882a593Smuzhiyun continue;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun clk = clk_get(dev, NULL);
69*4882a593Smuzhiyun if (IS_ERR(clk)) {
70*4882a593Smuzhiyun pr_err("%s:%d: failed to get UART%d clock\n",
71*4882a593Smuzhiyun __func__, __LINE__, i);
72*4882a593Smuzhiyun continue;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun clk_prepare_enable(clk);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun p->uartclk = clk_get_rate(clk);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun if (!p->membase && p->mapbase) {
80*4882a593Smuzhiyun p->membase = ioremap(p->mapbase, SZ_4K);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun if (p->membase)
83*4882a593Smuzhiyun p->flags &= ~UPF_IOREMAP;
84*4882a593Smuzhiyun else
85*4882a593Smuzhiyun pr_err("uart regs ioremap failed\n");
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun if (p->membase && p->type != PORT_AR7)
89*4882a593Smuzhiyun davinci_serial_reset(p);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun return ret;
92*4882a593Smuzhiyun }
93