1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Utility to set the DAVINCI MUX register from a table in mux.h
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Based on linux/arch/arm/plat-omap/mux.c:
7*4882a593Smuzhiyun * Copyright (C) 2003 - 2005 Nokia Corporation
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Written by Tony Lindgren
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * 2007 (c) MontaVista Software, Inc. This file is licensed under
12*4882a593Smuzhiyun * the terms of the GNU General Public License version 2. This program
13*4882a593Smuzhiyun * is licensed "as is" without any warranty of any kind, whether express
14*4882a593Smuzhiyun * or implied.
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * Copyright (C) 2008 Texas Instruments.
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <linux/io.h>
22*4882a593Smuzhiyun #include <linux/module.h>
23*4882a593Smuzhiyun #include <linux/spinlock.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include <mach/mux.h>
26*4882a593Smuzhiyun #include <mach/common.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static void __iomem *pinmux_base;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * Sets the DAVINCI MUX register based on the table
32*4882a593Smuzhiyun */
davinci_cfg_reg(const unsigned long index)33*4882a593Smuzhiyun int davinci_cfg_reg(const unsigned long index)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun static DEFINE_SPINLOCK(mux_spin_lock);
36*4882a593Smuzhiyun struct davinci_soc_info *soc_info = &davinci_soc_info;
37*4882a593Smuzhiyun unsigned long flags;
38*4882a593Smuzhiyun const struct mux_config *cfg;
39*4882a593Smuzhiyun unsigned int reg_orig = 0, reg = 0;
40*4882a593Smuzhiyun unsigned int mask, warn = 0;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (WARN_ON(!soc_info->pinmux_pins))
43*4882a593Smuzhiyun return -ENODEV;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun if (!pinmux_base) {
46*4882a593Smuzhiyun pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
47*4882a593Smuzhiyun if (WARN_ON(!pinmux_base))
48*4882a593Smuzhiyun return -ENOMEM;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun if (index >= soc_info->pinmux_pins_num) {
52*4882a593Smuzhiyun pr_err("Invalid pin mux index: %lu (%lu)\n",
53*4882a593Smuzhiyun index, soc_info->pinmux_pins_num);
54*4882a593Smuzhiyun dump_stack();
55*4882a593Smuzhiyun return -ENODEV;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun cfg = &soc_info->pinmux_pins[index];
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (cfg->name == NULL) {
61*4882a593Smuzhiyun pr_err("No entry for the specified index\n");
62*4882a593Smuzhiyun return -ENODEV;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Update the mux register in question */
66*4882a593Smuzhiyun if (cfg->mask) {
67*4882a593Smuzhiyun unsigned tmp1, tmp2;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun spin_lock_irqsave(&mux_spin_lock, flags);
70*4882a593Smuzhiyun reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun mask = (cfg->mask << cfg->mask_offset);
73*4882a593Smuzhiyun tmp1 = reg_orig & mask;
74*4882a593Smuzhiyun reg = reg_orig & ~mask;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun tmp2 = (cfg->mode << cfg->mask_offset);
77*4882a593Smuzhiyun reg |= tmp2;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun if (tmp1 != tmp2)
80*4882a593Smuzhiyun warn = 1;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun __raw_writel(reg, pinmux_base + cfg->mux_reg);
83*4882a593Smuzhiyun spin_unlock_irqrestore(&mux_spin_lock, flags);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun if (warn) {
87*4882a593Smuzhiyun #ifdef CONFIG_DAVINCI_MUX_WARNINGS
88*4882a593Smuzhiyun pr_warn("initialized %s\n", cfg->name);
89*4882a593Smuzhiyun #endif
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #ifdef CONFIG_DAVINCI_MUX_DEBUG
93*4882a593Smuzhiyun if (cfg->debug || warn) {
94*4882a593Smuzhiyun pr_warn("Setting register %s\n", cfg->name);
95*4882a593Smuzhiyun pr_warn(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
96*4882a593Smuzhiyun cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun #endif
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return 0;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun EXPORT_SYMBOL(davinci_cfg_reg);
103*4882a593Smuzhiyun
davinci_cfg_reg_list(const short pins[])104*4882a593Smuzhiyun int davinci_cfg_reg_list(const short pins[])
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun int i, error = -EINVAL;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun if (pins)
109*4882a593Smuzhiyun for (i = 0; pins[i] >= 0; i++) {
110*4882a593Smuzhiyun error = davinci_cfg_reg(pins[i]);
111*4882a593Smuzhiyun if (error)
112*4882a593Smuzhiyun break;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun return error;
116*4882a593Smuzhiyun }
117