1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * TI DaVinci platform support for power management. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or 7*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 8*4882a593Smuzhiyun * published by the Free Software Foundation version 2. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty 12*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13*4882a593Smuzhiyun * GNU General Public License for more details. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #ifndef _MACH_DAVINCI_PM_H 16*4882a593Smuzhiyun #define _MACH_DAVINCI_PM_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * Caution: Assembly code in sleep.S makes assumtion on the order 20*4882a593Smuzhiyun * of the members of this structure. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun struct davinci_pm_config { 23*4882a593Smuzhiyun void __iomem *ddr2_ctlr_base; 24*4882a593Smuzhiyun void __iomem *ddrpsc_reg_base; 25*4882a593Smuzhiyun int ddrpsc_num; 26*4882a593Smuzhiyun void __iomem *ddrpll_reg_base; 27*4882a593Smuzhiyun void __iomem *deepsleep_reg; 28*4882a593Smuzhiyun void __iomem *cpupll_reg_base; 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * Note on SLEEPCOUNT: 31*4882a593Smuzhiyun * The SLEEPCOUNT feature is mainly intended for cases in which 32*4882a593Smuzhiyun * the internal oscillator is used. The internal oscillator is 33*4882a593Smuzhiyun * fully disabled in deep sleep mode. When you exist deep sleep 34*4882a593Smuzhiyun * mode, the oscillator will be turned on and will generate very 35*4882a593Smuzhiyun * small oscillations which will not be detected by the deep sleep 36*4882a593Smuzhiyun * counter. Eventually those oscillations will grow to an amplitude 37*4882a593Smuzhiyun * large enough to start incrementing the deep sleep counter. 38*4882a593Smuzhiyun * In this case recommendation from hardware engineers is that the 39*4882a593Smuzhiyun * SLEEPCOUNT be set to 4096. This means that 4096 valid clock cycles 40*4882a593Smuzhiyun * must be detected before the clock is passed to the rest of the 41*4882a593Smuzhiyun * system. 42*4882a593Smuzhiyun * In the case that the internal oscillator is not used and the 43*4882a593Smuzhiyun * clock is generated externally, the SLEEPCOUNT value can be very 44*4882a593Smuzhiyun * small since the clock input is assumed to be stable before SoC 45*4882a593Smuzhiyun * is taken out of deepsleep mode. A value of 128 would be more than 46*4882a593Smuzhiyun * adequate. 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun int sleepcount; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun extern unsigned int davinci_cpu_suspend_sz; 52*4882a593Smuzhiyun extern void davinci_cpu_suspend(struct davinci_pm_config *); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif 55