1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Header for code common to all DaVinci machines. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * 2007 (c) MontaVista Software, Inc. This file is licensed under 7*4882a593Smuzhiyun * the terms of the GNU General Public License version 2. This program 8*4882a593Smuzhiyun * is licensed "as is" without any warranty of any kind, whether express 9*4882a593Smuzhiyun * or implied. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H 13*4882a593Smuzhiyun #define __ARCH_ARM_MACH_DAVINCI_COMMON_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <linux/clk.h> 16*4882a593Smuzhiyun #include <linux/compiler.h> 17*4882a593Smuzhiyun #include <linux/types.h> 18*4882a593Smuzhiyun #include <linux/reboot.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <asm/irq.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define DAVINCI_INTC_START NR_IRQS 23*4882a593Smuzhiyun #define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum)) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun struct davinci_gpio_controller; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * SoC info passed into common davinci modules. 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * Base addresses in this structure should be physical and not virtual. 31*4882a593Smuzhiyun * Modules that take such base addresses, should internally ioremap() them to 32*4882a593Smuzhiyun * use. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun struct davinci_soc_info { 35*4882a593Smuzhiyun struct map_desc *io_desc; 36*4882a593Smuzhiyun unsigned long io_desc_num; 37*4882a593Smuzhiyun u32 cpu_id; 38*4882a593Smuzhiyun u32 jtag_id; 39*4882a593Smuzhiyun u32 jtag_id_reg; 40*4882a593Smuzhiyun struct davinci_id *ids; 41*4882a593Smuzhiyun unsigned long ids_num; 42*4882a593Smuzhiyun u32 pinmux_base; 43*4882a593Smuzhiyun const struct mux_config *pinmux_pins; 44*4882a593Smuzhiyun unsigned long pinmux_pins_num; 45*4882a593Smuzhiyun int gpio_type; 46*4882a593Smuzhiyun u32 gpio_base; 47*4882a593Smuzhiyun unsigned gpio_num; 48*4882a593Smuzhiyun unsigned gpio_irq; 49*4882a593Smuzhiyun unsigned gpio_unbanked; 50*4882a593Smuzhiyun struct davinci_gpio_controller *gpio_ctlrs; 51*4882a593Smuzhiyun int gpio_ctlrs_num; 52*4882a593Smuzhiyun struct emac_platform_data *emac_pdata; 53*4882a593Smuzhiyun dma_addr_t sram_dma; 54*4882a593Smuzhiyun unsigned sram_len; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun extern struct davinci_soc_info davinci_soc_info; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun extern void davinci_common_init(const struct davinci_soc_info *soc_info); 60*4882a593Smuzhiyun extern void davinci_init_ide(void); 61*4882a593Smuzhiyun void davinci_init_late(void); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #ifdef CONFIG_CPU_FREQ 64*4882a593Smuzhiyun int davinci_cpufreq_init(void); 65*4882a593Smuzhiyun #else davinci_cpufreq_init(void)66*4882a593Smuzhiyunstatic inline int davinci_cpufreq_init(void) { return 0; } 67*4882a593Smuzhiyun #endif 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #ifdef CONFIG_SUSPEND 70*4882a593Smuzhiyun int davinci_pm_init(void); 71*4882a593Smuzhiyun #else davinci_pm_init(void)72*4882a593Smuzhiyunstatic inline int davinci_pm_init(void) { return 0; } 73*4882a593Smuzhiyun #endif 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun void __init pdata_quirks_init(void); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define SRAM_SIZE SZ_128K 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ 80