xref: /OK3568_Linux_fs/kernel/arch/arm/mach-davinci/board-dm355-evm.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * TI DaVinci EVM board support
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Author: Kevin Hilman, Deep Root Systems, LLC
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * 2007 (c) MontaVista Software, Inc. This file is licensed under
7*4882a593Smuzhiyun  * the terms of the GNU General Public License version 2. This program
8*4882a593Smuzhiyun  * is licensed "as is" without any warranty of any kind, whether express
9*4882a593Smuzhiyun  * or implied.
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/err.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
16*4882a593Smuzhiyun #include <linux/mtd/partitions.h>
17*4882a593Smuzhiyun #include <linux/mtd/rawnand.h>
18*4882a593Smuzhiyun #include <linux/i2c.h>
19*4882a593Smuzhiyun #include <linux/gpio.h>
20*4882a593Smuzhiyun #include <linux/gpio/machine.h>
21*4882a593Smuzhiyun #include <linux/clk.h>
22*4882a593Smuzhiyun #include <linux/dm9000.h>
23*4882a593Smuzhiyun #include <linux/videodev2.h>
24*4882a593Smuzhiyun #include <media/i2c/tvp514x.h>
25*4882a593Smuzhiyun #include <linux/spi/spi.h>
26*4882a593Smuzhiyun #include <linux/spi/eeprom.h>
27*4882a593Smuzhiyun #include <linux/platform_data/gpio-davinci.h>
28*4882a593Smuzhiyun #include <linux/platform_data/i2c-davinci.h>
29*4882a593Smuzhiyun #include <linux/platform_data/mtd-davinci.h>
30*4882a593Smuzhiyun #include <linux/platform_data/mmc-davinci.h>
31*4882a593Smuzhiyun #include <linux/platform_data/usb-davinci.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #include <asm/mach-types.h>
34*4882a593Smuzhiyun #include <asm/mach/arch.h>
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #include <mach/serial.h>
37*4882a593Smuzhiyun #include <mach/common.h>
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #include "davinci.h"
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /* NOTE:  this is geared for the standard config, with a socketed
42*4882a593Smuzhiyun  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
43*4882a593Smuzhiyun  * swap chips, maybe with a different block size, partitioning may
44*4882a593Smuzhiyun  * need to be changed.
45*4882a593Smuzhiyun  */
46*4882a593Smuzhiyun #define NAND_BLOCK_SIZE		SZ_128K
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun static struct mtd_partition davinci_nand_partitions[] = {
49*4882a593Smuzhiyun 	{
50*4882a593Smuzhiyun 		/* UBL (a few copies) plus U-Boot */
51*4882a593Smuzhiyun 		.name		= "bootloader",
52*4882a593Smuzhiyun 		.offset		= 0,
53*4882a593Smuzhiyun 		.size		= 15 * NAND_BLOCK_SIZE,
54*4882a593Smuzhiyun 		.mask_flags	= MTD_WRITEABLE, /* force read-only */
55*4882a593Smuzhiyun 	}, {
56*4882a593Smuzhiyun 		/* U-Boot environment */
57*4882a593Smuzhiyun 		.name		= "params",
58*4882a593Smuzhiyun 		.offset		= MTDPART_OFS_APPEND,
59*4882a593Smuzhiyun 		.size		= 1 * NAND_BLOCK_SIZE,
60*4882a593Smuzhiyun 		.mask_flags	= 0,
61*4882a593Smuzhiyun 	}, {
62*4882a593Smuzhiyun 		.name		= "kernel",
63*4882a593Smuzhiyun 		.offset		= MTDPART_OFS_APPEND,
64*4882a593Smuzhiyun 		.size		= SZ_4M,
65*4882a593Smuzhiyun 		.mask_flags	= 0,
66*4882a593Smuzhiyun 	}, {
67*4882a593Smuzhiyun 		.name		= "filesystem1",
68*4882a593Smuzhiyun 		.offset		= MTDPART_OFS_APPEND,
69*4882a593Smuzhiyun 		.size		= SZ_512M,
70*4882a593Smuzhiyun 		.mask_flags	= 0,
71*4882a593Smuzhiyun 	}, {
72*4882a593Smuzhiyun 		.name		= "filesystem2",
73*4882a593Smuzhiyun 		.offset		= MTDPART_OFS_APPEND,
74*4882a593Smuzhiyun 		.size		= MTDPART_SIZ_FULL,
75*4882a593Smuzhiyun 		.mask_flags	= 0,
76*4882a593Smuzhiyun 	}
77*4882a593Smuzhiyun 	/* two blocks with bad block table (and mirror) at the end */
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun static struct davinci_nand_pdata davinci_nand_data = {
81*4882a593Smuzhiyun 	.core_chipsel		= 0,
82*4882a593Smuzhiyun 	.mask_chipsel		= BIT(14),
83*4882a593Smuzhiyun 	.parts			= davinci_nand_partitions,
84*4882a593Smuzhiyun 	.nr_parts		= ARRAY_SIZE(davinci_nand_partitions),
85*4882a593Smuzhiyun 	.engine_type		= NAND_ECC_ENGINE_TYPE_ON_HOST,
86*4882a593Smuzhiyun 	.bbt_options		= NAND_BBT_USE_FLASH,
87*4882a593Smuzhiyun 	.ecc_bits		= 4,
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun static struct resource davinci_nand_resources[] = {
91*4882a593Smuzhiyun 	{
92*4882a593Smuzhiyun 		.start		= DM355_ASYNC_EMIF_DATA_CE0_BASE,
93*4882a593Smuzhiyun 		.end		= DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
94*4882a593Smuzhiyun 		.flags		= IORESOURCE_MEM,
95*4882a593Smuzhiyun 	}, {
96*4882a593Smuzhiyun 		.start		= DM355_ASYNC_EMIF_CONTROL_BASE,
97*4882a593Smuzhiyun 		.end		= DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
98*4882a593Smuzhiyun 		.flags		= IORESOURCE_MEM,
99*4882a593Smuzhiyun 	},
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun static struct platform_device davinci_nand_device = {
103*4882a593Smuzhiyun 	.name			= "davinci_nand",
104*4882a593Smuzhiyun 	.id			= 0,
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	.num_resources		= ARRAY_SIZE(davinci_nand_resources),
107*4882a593Smuzhiyun 	.resource		= davinci_nand_resources,
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	.dev			= {
110*4882a593Smuzhiyun 		.platform_data	= &davinci_nand_data,
111*4882a593Smuzhiyun 	},
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun #define DM355_I2C_SDA_PIN	GPIO_TO_PIN(0, 15)
115*4882a593Smuzhiyun #define DM355_I2C_SCL_PIN	GPIO_TO_PIN(0, 14)
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
118*4882a593Smuzhiyun 	.dev_id = "i2c_davinci.1",
119*4882a593Smuzhiyun 	.table = {
120*4882a593Smuzhiyun 		GPIO_LOOKUP("davinci_gpio", DM355_I2C_SDA_PIN, "sda",
121*4882a593Smuzhiyun 			    GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
122*4882a593Smuzhiyun 		GPIO_LOOKUP("davinci_gpio", DM355_I2C_SCL_PIN, "scl",
123*4882a593Smuzhiyun 			    GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
124*4882a593Smuzhiyun 		{ }
125*4882a593Smuzhiyun 	},
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun static struct davinci_i2c_platform_data i2c_pdata = {
129*4882a593Smuzhiyun 	.bus_freq	= 400	/* kHz */,
130*4882a593Smuzhiyun 	.bus_delay	= 0	/* usec */,
131*4882a593Smuzhiyun 	.gpio_recovery	= true,
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun static int dm355evm_mmc_gpios = -EINVAL;
135*4882a593Smuzhiyun 
dm355evm_mmcsd_gpios(unsigned gpio)136*4882a593Smuzhiyun static void dm355evm_mmcsd_gpios(unsigned gpio)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun 	gpio_request(gpio + 0, "mmc0_ro");
139*4882a593Smuzhiyun 	gpio_request(gpio + 1, "mmc0_cd");
140*4882a593Smuzhiyun 	gpio_request(gpio + 2, "mmc1_ro");
141*4882a593Smuzhiyun 	gpio_request(gpio + 3, "mmc1_cd");
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	/* we "know" these are input-only so we don't
144*4882a593Smuzhiyun 	 * need to call gpio_direction_input()
145*4882a593Smuzhiyun 	 */
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	dm355evm_mmc_gpios = gpio;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun static struct i2c_board_info dm355evm_i2c_info[] = {
151*4882a593Smuzhiyun 	{	I2C_BOARD_INFO("dm355evm_msp", 0x25),
152*4882a593Smuzhiyun 		.platform_data = dm355evm_mmcsd_gpios,
153*4882a593Smuzhiyun 	},
154*4882a593Smuzhiyun 	/* { plus irq  }, */
155*4882a593Smuzhiyun 	{ I2C_BOARD_INFO("tlv320aic33", 0x1b), },
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun 
evm_init_i2c(void)158*4882a593Smuzhiyun static void __init evm_init_i2c(void)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun 	gpiod_add_lookup_table(&i2c_recovery_gpiod_table);
161*4882a593Smuzhiyun 	davinci_init_i2c(&i2c_pdata);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	gpio_request(5, "dm355evm_msp");
164*4882a593Smuzhiyun 	gpio_direction_input(5);
165*4882a593Smuzhiyun 	dm355evm_i2c_info[0].irq = gpio_to_irq(5);
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	i2c_register_board_info(1, dm355evm_i2c_info,
168*4882a593Smuzhiyun 			ARRAY_SIZE(dm355evm_i2c_info));
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun static struct resource dm355evm_dm9000_rsrc[] = {
172*4882a593Smuzhiyun 	{
173*4882a593Smuzhiyun 		/* addr */
174*4882a593Smuzhiyun 		.start	= 0x04014000,
175*4882a593Smuzhiyun 		.end	= 0x04014001,
176*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
177*4882a593Smuzhiyun 	}, {
178*4882a593Smuzhiyun 		/* data */
179*4882a593Smuzhiyun 		.start	= 0x04014002,
180*4882a593Smuzhiyun 		.end	= 0x04014003,
181*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
182*4882a593Smuzhiyun 	}, {
183*4882a593Smuzhiyun 		.flags	= IORESOURCE_IRQ
184*4882a593Smuzhiyun 			| IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */,
185*4882a593Smuzhiyun 	},
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun static struct dm9000_plat_data dm335evm_dm9000_platdata;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun static struct platform_device dm355evm_dm9000 = {
191*4882a593Smuzhiyun 	.name		= "dm9000",
192*4882a593Smuzhiyun 	.id		= -1,
193*4882a593Smuzhiyun 	.resource	= dm355evm_dm9000_rsrc,
194*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(dm355evm_dm9000_rsrc),
195*4882a593Smuzhiyun 	.dev		= {
196*4882a593Smuzhiyun 		.platform_data = &dm335evm_dm9000_platdata,
197*4882a593Smuzhiyun 	},
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun static struct tvp514x_platform_data tvp5146_pdata = {
201*4882a593Smuzhiyun 	.clk_polarity = 0,
202*4882a593Smuzhiyun 	.hs_polarity = 1,
203*4882a593Smuzhiyun 	.vs_polarity = 1
204*4882a593Smuzhiyun };
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun #define TVP514X_STD_ALL	(V4L2_STD_NTSC | V4L2_STD_PAL)
207*4882a593Smuzhiyun /* Inputs available at the TVP5146 */
208*4882a593Smuzhiyun static struct v4l2_input tvp5146_inputs[] = {
209*4882a593Smuzhiyun 	{
210*4882a593Smuzhiyun 		.index = 0,
211*4882a593Smuzhiyun 		.name = "Composite",
212*4882a593Smuzhiyun 		.type = V4L2_INPUT_TYPE_CAMERA,
213*4882a593Smuzhiyun 		.std = TVP514X_STD_ALL,
214*4882a593Smuzhiyun 	},
215*4882a593Smuzhiyun 	{
216*4882a593Smuzhiyun 		.index = 1,
217*4882a593Smuzhiyun 		.name = "S-Video",
218*4882a593Smuzhiyun 		.type = V4L2_INPUT_TYPE_CAMERA,
219*4882a593Smuzhiyun 		.std = TVP514X_STD_ALL,
220*4882a593Smuzhiyun 	},
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun /*
224*4882a593Smuzhiyun  * this is the route info for connecting each input to decoder
225*4882a593Smuzhiyun  * ouput that goes to vpfe. There is a one to one correspondence
226*4882a593Smuzhiyun  * with tvp5146_inputs
227*4882a593Smuzhiyun  */
228*4882a593Smuzhiyun static struct vpfe_route tvp5146_routes[] = {
229*4882a593Smuzhiyun 	{
230*4882a593Smuzhiyun 		.input = INPUT_CVBS_VI2B,
231*4882a593Smuzhiyun 		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
232*4882a593Smuzhiyun 	},
233*4882a593Smuzhiyun 	{
234*4882a593Smuzhiyun 		.input = INPUT_SVIDEO_VI2C_VI1C,
235*4882a593Smuzhiyun 		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
236*4882a593Smuzhiyun 	},
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun static struct vpfe_subdev_info vpfe_sub_devs[] = {
240*4882a593Smuzhiyun 	{
241*4882a593Smuzhiyun 		.name = "tvp5146",
242*4882a593Smuzhiyun 		.grp_id = 0,
243*4882a593Smuzhiyun 		.num_inputs = ARRAY_SIZE(tvp5146_inputs),
244*4882a593Smuzhiyun 		.inputs = tvp5146_inputs,
245*4882a593Smuzhiyun 		.routes = tvp5146_routes,
246*4882a593Smuzhiyun 		.can_route = 1,
247*4882a593Smuzhiyun 		.ccdc_if_params = {
248*4882a593Smuzhiyun 			.if_type = VPFE_BT656,
249*4882a593Smuzhiyun 			.hdpol = VPFE_PINPOL_POSITIVE,
250*4882a593Smuzhiyun 			.vdpol = VPFE_PINPOL_POSITIVE,
251*4882a593Smuzhiyun 		},
252*4882a593Smuzhiyun 		.board_info = {
253*4882a593Smuzhiyun 			I2C_BOARD_INFO("tvp5146", 0x5d),
254*4882a593Smuzhiyun 			.platform_data = &tvp5146_pdata,
255*4882a593Smuzhiyun 		},
256*4882a593Smuzhiyun 	}
257*4882a593Smuzhiyun };
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun static struct vpfe_config vpfe_cfg = {
260*4882a593Smuzhiyun 	.num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
261*4882a593Smuzhiyun 	.i2c_adapter_id = 1,
262*4882a593Smuzhiyun 	.sub_devs = vpfe_sub_devs,
263*4882a593Smuzhiyun 	.card_name = "DM355 EVM",
264*4882a593Smuzhiyun 	.ccdc = "DM355 CCDC",
265*4882a593Smuzhiyun };
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun /* venc standards timings */
268*4882a593Smuzhiyun static struct vpbe_enc_mode_info dm355evm_enc_preset_timing[] = {
269*4882a593Smuzhiyun 	{
270*4882a593Smuzhiyun 		.name		= "ntsc",
271*4882a593Smuzhiyun 		.timings_type	= VPBE_ENC_STD,
272*4882a593Smuzhiyun 		.std_id		= V4L2_STD_NTSC,
273*4882a593Smuzhiyun 		.interlaced	= 1,
274*4882a593Smuzhiyun 		.xres		= 720,
275*4882a593Smuzhiyun 		.yres		= 480,
276*4882a593Smuzhiyun 		.aspect		= {11, 10},
277*4882a593Smuzhiyun 		.fps		= {30000, 1001},
278*4882a593Smuzhiyun 		.left_margin	= 0x79,
279*4882a593Smuzhiyun 		.upper_margin	= 0x10,
280*4882a593Smuzhiyun 	},
281*4882a593Smuzhiyun 	{
282*4882a593Smuzhiyun 		.name		= "pal",
283*4882a593Smuzhiyun 		.timings_type	= VPBE_ENC_STD,
284*4882a593Smuzhiyun 		.std_id		= V4L2_STD_PAL,
285*4882a593Smuzhiyun 		.interlaced	= 1,
286*4882a593Smuzhiyun 		.xres		= 720,
287*4882a593Smuzhiyun 		.yres		= 576,
288*4882a593Smuzhiyun 		.aspect		= {54, 59},
289*4882a593Smuzhiyun 		.fps		= {25, 1},
290*4882a593Smuzhiyun 		.left_margin	= 0x7E,
291*4882a593Smuzhiyun 		.upper_margin	= 0x16
292*4882a593Smuzhiyun 	},
293*4882a593Smuzhiyun };
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun #define VENC_STD_ALL	(V4L2_STD_NTSC | V4L2_STD_PAL)
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun /*
298*4882a593Smuzhiyun  * The outputs available from VPBE + ecnoders. Keep the
299*4882a593Smuzhiyun  * the order same as that of encoders. First those from venc followed by that
300*4882a593Smuzhiyun  * from encoders. Index in the output refers to index on a particular encoder.
301*4882a593Smuzhiyun  * Driver uses this index to pass it to encoder when it supports more than
302*4882a593Smuzhiyun  * one output. Application uses index of the array to set an output.
303*4882a593Smuzhiyun  */
304*4882a593Smuzhiyun static struct vpbe_output dm355evm_vpbe_outputs[] = {
305*4882a593Smuzhiyun 	{
306*4882a593Smuzhiyun 		.output		= {
307*4882a593Smuzhiyun 			.index		= 0,
308*4882a593Smuzhiyun 			.name		= "Composite",
309*4882a593Smuzhiyun 			.type		= V4L2_OUTPUT_TYPE_ANALOG,
310*4882a593Smuzhiyun 			.std		= VENC_STD_ALL,
311*4882a593Smuzhiyun 			.capabilities	= V4L2_OUT_CAP_STD,
312*4882a593Smuzhiyun 		},
313*4882a593Smuzhiyun 		.subdev_name	= DM355_VPBE_VENC_SUBDEV_NAME,
314*4882a593Smuzhiyun 		.default_mode	= "ntsc",
315*4882a593Smuzhiyun 		.num_modes	= ARRAY_SIZE(dm355evm_enc_preset_timing),
316*4882a593Smuzhiyun 		.modes		= dm355evm_enc_preset_timing,
317*4882a593Smuzhiyun 		.if_params	= MEDIA_BUS_FMT_FIXED,
318*4882a593Smuzhiyun 	},
319*4882a593Smuzhiyun };
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun static struct vpbe_config dm355evm_display_cfg = {
322*4882a593Smuzhiyun 	.module_name	= "dm355-vpbe-display",
323*4882a593Smuzhiyun 	.i2c_adapter_id	= 1,
324*4882a593Smuzhiyun 	.osd		= {
325*4882a593Smuzhiyun 		.module_name	= DM355_VPBE_OSD_SUBDEV_NAME,
326*4882a593Smuzhiyun 	},
327*4882a593Smuzhiyun 	.venc		= {
328*4882a593Smuzhiyun 		.module_name	= DM355_VPBE_VENC_SUBDEV_NAME,
329*4882a593Smuzhiyun 	},
330*4882a593Smuzhiyun 	.num_outputs	= ARRAY_SIZE(dm355evm_vpbe_outputs),
331*4882a593Smuzhiyun 	.outputs	= dm355evm_vpbe_outputs,
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun static struct platform_device *davinci_evm_devices[] __initdata = {
335*4882a593Smuzhiyun 	&dm355evm_dm9000,
336*4882a593Smuzhiyun 	&davinci_nand_device,
337*4882a593Smuzhiyun };
338*4882a593Smuzhiyun 
dm355_evm_map_io(void)339*4882a593Smuzhiyun static void __init dm355_evm_map_io(void)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun 	dm355_init();
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun 
dm355evm_mmc_get_cd(int module)344*4882a593Smuzhiyun static int dm355evm_mmc_get_cd(int module)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun 	if (!gpio_is_valid(dm355evm_mmc_gpios))
347*4882a593Smuzhiyun 		return -ENXIO;
348*4882a593Smuzhiyun 	/* low == card present */
349*4882a593Smuzhiyun 	return !gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 1);
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun 
dm355evm_mmc_get_ro(int module)352*4882a593Smuzhiyun static int dm355evm_mmc_get_ro(int module)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun 	if (!gpio_is_valid(dm355evm_mmc_gpios))
355*4882a593Smuzhiyun 		return -ENXIO;
356*4882a593Smuzhiyun 	/* high == card's write protect switch active */
357*4882a593Smuzhiyun 	return gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 0);
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun static struct davinci_mmc_config dm355evm_mmc_config = {
361*4882a593Smuzhiyun 	.get_cd		= dm355evm_mmc_get_cd,
362*4882a593Smuzhiyun 	.get_ro		= dm355evm_mmc_get_ro,
363*4882a593Smuzhiyun 	.wires		= 4,
364*4882a593Smuzhiyun 	.max_freq       = 50000000,
365*4882a593Smuzhiyun 	.caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
366*4882a593Smuzhiyun };
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun /* Don't connect anything to J10 unless you're only using USB host
369*4882a593Smuzhiyun  * mode *and* have to do so with some kind of gender-bender.  If
370*4882a593Smuzhiyun  * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
371*4882a593Smuzhiyun  * the ID pin won't need any help.
372*4882a593Smuzhiyun  */
373*4882a593Smuzhiyun #define USB_ID_VALUE	1	/* ID pulled low */
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun static struct spi_eeprom at25640a = {
376*4882a593Smuzhiyun 	.byte_len	= SZ_64K / 8,
377*4882a593Smuzhiyun 	.name		= "at25640a",
378*4882a593Smuzhiyun 	.page_size	= 32,
379*4882a593Smuzhiyun 	.flags		= EE_ADDR2,
380*4882a593Smuzhiyun };
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun static const struct spi_board_info dm355_evm_spi_info[] __initconst = {
383*4882a593Smuzhiyun 	{
384*4882a593Smuzhiyun 		.modalias	= "at25",
385*4882a593Smuzhiyun 		.platform_data	= &at25640a,
386*4882a593Smuzhiyun 		.max_speed_hz	= 10 * 1000 * 1000,	/* at 3v3 */
387*4882a593Smuzhiyun 		.bus_num	= 0,
388*4882a593Smuzhiyun 		.chip_select	= 0,
389*4882a593Smuzhiyun 		.mode		= SPI_MODE_0,
390*4882a593Smuzhiyun 	},
391*4882a593Smuzhiyun };
392*4882a593Smuzhiyun 
dm355_evm_init(void)393*4882a593Smuzhiyun static __init void dm355_evm_init(void)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun 	struct clk *aemif;
396*4882a593Smuzhiyun 	int ret;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	dm355_register_clocks();
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	ret = dm355_gpio_register();
401*4882a593Smuzhiyun 	if (ret)
402*4882a593Smuzhiyun 		pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	gpio_request(1, "dm9000");
405*4882a593Smuzhiyun 	gpio_direction_input(1);
406*4882a593Smuzhiyun 	dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1);
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	aemif = clk_get(&dm355evm_dm9000.dev, "aemif");
409*4882a593Smuzhiyun 	if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n"))
410*4882a593Smuzhiyun 		clk_prepare_enable(aemif);
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	platform_add_devices(davinci_evm_devices,
413*4882a593Smuzhiyun 			     ARRAY_SIZE(davinci_evm_devices));
414*4882a593Smuzhiyun 	evm_init_i2c();
415*4882a593Smuzhiyun 	davinci_serial_init(dm355_serial_device);
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	/* NOTE:  NAND flash timings set by the UBL are slower than
418*4882a593Smuzhiyun 	 * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
419*4882a593Smuzhiyun 	 * but could be 0x0400008c for about 25% faster page reads.
420*4882a593Smuzhiyun 	 */
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	gpio_request(2, "usb_id_toggle");
423*4882a593Smuzhiyun 	gpio_direction_output(2, USB_ID_VALUE);
424*4882a593Smuzhiyun 	/* irlml6401 switches over 1A in under 8 msec */
425*4882a593Smuzhiyun 	davinci_setup_usb(1000, 8);
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	davinci_setup_mmc(0, &dm355evm_mmc_config);
428*4882a593Smuzhiyun 	davinci_setup_mmc(1, &dm355evm_mmc_config);
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	dm355_init_video(&vpfe_cfg, &dm355evm_display_cfg);
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	dm355_init_spi0(BIT(0), dm355_evm_spi_info,
433*4882a593Smuzhiyun 			ARRAY_SIZE(dm355_evm_spi_info));
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	/* DM335 EVM uses ASP1; line-out is a stereo mini-jack */
436*4882a593Smuzhiyun 	dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN);
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
440*4882a593Smuzhiyun 	.atag_offset  = 0x100,
441*4882a593Smuzhiyun 	.map_io	      = dm355_evm_map_io,
442*4882a593Smuzhiyun 	.init_irq     = dm355_init_irq,
443*4882a593Smuzhiyun 	.init_time	= dm355_init_time,
444*4882a593Smuzhiyun 	.init_machine = dm355_evm_init,
445*4882a593Smuzhiyun 	.init_late	= davinci_init_late,
446*4882a593Smuzhiyun 	.dma_zone_size	= SZ_128M,
447*4882a593Smuzhiyun MACHINE_END
448