1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * TI DA850/OMAP-L138 EVM board
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Derived from: arch/arm/mach-davinci/board-da830-evm.c
7*4882a593Smuzhiyun * Original Copyrights follow:
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
10*4882a593Smuzhiyun * the terms of the GNU General Public License version 2. This program
11*4882a593Smuzhiyun * is licensed "as is" without any warranty of any kind, whether express
12*4882a593Smuzhiyun * or implied.
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun #include <linux/console.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/gpio.h>
17*4882a593Smuzhiyun #include <linux/gpio_keys.h>
18*4882a593Smuzhiyun #include <linux/gpio/machine.h>
19*4882a593Smuzhiyun #include <linux/init.h>
20*4882a593Smuzhiyun #include <linux/kernel.h>
21*4882a593Smuzhiyun #include <linux/leds.h>
22*4882a593Smuzhiyun #include <linux/i2c.h>
23*4882a593Smuzhiyun #include <linux/platform_data/pca953x.h>
24*4882a593Smuzhiyun #include <linux/input.h>
25*4882a593Smuzhiyun #include <linux/input/tps6507x-ts.h>
26*4882a593Smuzhiyun #include <linux/mfd/tps6507x.h>
27*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
28*4882a593Smuzhiyun #include <linux/mtd/rawnand.h>
29*4882a593Smuzhiyun #include <linux/mtd/partitions.h>
30*4882a593Smuzhiyun #include <linux/nvmem-provider.h>
31*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
32*4882a593Smuzhiyun #include <linux/platform_device.h>
33*4882a593Smuzhiyun #include <linux/platform_data/gpio-davinci.h>
34*4882a593Smuzhiyun #include <linux/platform_data/mtd-davinci.h>
35*4882a593Smuzhiyun #include <linux/platform_data/mtd-davinci-aemif.h>
36*4882a593Smuzhiyun #include <linux/platform_data/ti-aemif.h>
37*4882a593Smuzhiyun #include <linux/platform_data/spi-davinci.h>
38*4882a593Smuzhiyun #include <linux/platform_data/uio_pruss.h>
39*4882a593Smuzhiyun #include <linux/property.h>
40*4882a593Smuzhiyun #include <linux/regulator/machine.h>
41*4882a593Smuzhiyun #include <linux/regulator/tps6507x.h>
42*4882a593Smuzhiyun #include <linux/regulator/fixed.h>
43*4882a593Smuzhiyun #include <linux/spi/spi.h>
44*4882a593Smuzhiyun #include <linux/spi/flash.h>
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #include <mach/common.h>
47*4882a593Smuzhiyun #include <mach/da8xx.h>
48*4882a593Smuzhiyun #include <mach/mux.h>
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #include "irqs.h"
51*4882a593Smuzhiyun #include "sram.h"
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #include <asm/mach-types.h>
54*4882a593Smuzhiyun #include <asm/mach/arch.h>
55*4882a593Smuzhiyun #include <asm/system_info.h>
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #include <media/i2c/tvp514x.h>
58*4882a593Smuzhiyun #include <media/i2c/adv7343.h>
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define DA850_EVM_PHY_ID "davinci_mdio-0:00"
61*4882a593Smuzhiyun #define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
62*4882a593Smuzhiyun #define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6)
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static struct mtd_partition da850evm_spiflash_part[] = {
67*4882a593Smuzhiyun [0] = {
68*4882a593Smuzhiyun .name = "UBL",
69*4882a593Smuzhiyun .offset = 0,
70*4882a593Smuzhiyun .size = SZ_64K,
71*4882a593Smuzhiyun .mask_flags = MTD_WRITEABLE,
72*4882a593Smuzhiyun },
73*4882a593Smuzhiyun [1] = {
74*4882a593Smuzhiyun .name = "U-Boot",
75*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
76*4882a593Smuzhiyun .size = SZ_512K,
77*4882a593Smuzhiyun .mask_flags = MTD_WRITEABLE,
78*4882a593Smuzhiyun },
79*4882a593Smuzhiyun [2] = {
80*4882a593Smuzhiyun .name = "U-Boot-Env",
81*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
82*4882a593Smuzhiyun .size = SZ_64K,
83*4882a593Smuzhiyun .mask_flags = MTD_WRITEABLE,
84*4882a593Smuzhiyun },
85*4882a593Smuzhiyun [3] = {
86*4882a593Smuzhiyun .name = "Kernel",
87*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
88*4882a593Smuzhiyun .size = SZ_2M + SZ_512K,
89*4882a593Smuzhiyun .mask_flags = 0,
90*4882a593Smuzhiyun },
91*4882a593Smuzhiyun [4] = {
92*4882a593Smuzhiyun .name = "Filesystem",
93*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
94*4882a593Smuzhiyun .size = SZ_4M,
95*4882a593Smuzhiyun .mask_flags = 0,
96*4882a593Smuzhiyun },
97*4882a593Smuzhiyun [5] = {
98*4882a593Smuzhiyun .name = "MAC-Address",
99*4882a593Smuzhiyun .offset = SZ_8M - SZ_64K,
100*4882a593Smuzhiyun .size = SZ_64K,
101*4882a593Smuzhiyun .mask_flags = MTD_WRITEABLE,
102*4882a593Smuzhiyun },
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun static struct nvmem_cell_info da850evm_nvmem_cells[] = {
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun .name = "macaddr",
108*4882a593Smuzhiyun .offset = 0x0,
109*4882a593Smuzhiyun .bytes = ETH_ALEN,
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun static struct nvmem_cell_table da850evm_nvmem_cell_table = {
114*4882a593Smuzhiyun /*
115*4882a593Smuzhiyun * The nvmem name differs from the partition name because of the
116*4882a593Smuzhiyun * internal works of the nvmem framework.
117*4882a593Smuzhiyun */
118*4882a593Smuzhiyun .nvmem_name = "MAC-Address0",
119*4882a593Smuzhiyun .cells = da850evm_nvmem_cells,
120*4882a593Smuzhiyun .ncells = ARRAY_SIZE(da850evm_nvmem_cells),
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun static struct nvmem_cell_lookup da850evm_nvmem_cell_lookup = {
124*4882a593Smuzhiyun .nvmem_name = "MAC-Address0",
125*4882a593Smuzhiyun .cell_name = "macaddr",
126*4882a593Smuzhiyun .dev_id = "davinci_emac.1",
127*4882a593Smuzhiyun .con_id = "mac-address",
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun static struct flash_platform_data da850evm_spiflash_data = {
131*4882a593Smuzhiyun .name = "m25p80",
132*4882a593Smuzhiyun .parts = da850evm_spiflash_part,
133*4882a593Smuzhiyun .nr_parts = ARRAY_SIZE(da850evm_spiflash_part),
134*4882a593Smuzhiyun .type = "m25p64",
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun static struct davinci_spi_config da850evm_spiflash_cfg = {
138*4882a593Smuzhiyun .io_type = SPI_IO_TYPE_DMA,
139*4882a593Smuzhiyun .c2tdelay = 8,
140*4882a593Smuzhiyun .t2cdelay = 8,
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun static struct spi_board_info da850evm_spi_info[] = {
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun .modalias = "m25p80",
146*4882a593Smuzhiyun .platform_data = &da850evm_spiflash_data,
147*4882a593Smuzhiyun .controller_data = &da850evm_spiflash_cfg,
148*4882a593Smuzhiyun .mode = SPI_MODE_0,
149*4882a593Smuzhiyun .max_speed_hz = 30000000,
150*4882a593Smuzhiyun .bus_num = 1,
151*4882a593Smuzhiyun .chip_select = 0,
152*4882a593Smuzhiyun },
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun static struct mtd_partition da850_evm_norflash_partition[] = {
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun .name = "bootloaders + env",
158*4882a593Smuzhiyun .offset = 0,
159*4882a593Smuzhiyun .size = SZ_512K,
160*4882a593Smuzhiyun .mask_flags = MTD_WRITEABLE,
161*4882a593Smuzhiyun },
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun .name = "kernel",
164*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
165*4882a593Smuzhiyun .size = SZ_2M,
166*4882a593Smuzhiyun .mask_flags = 0,
167*4882a593Smuzhiyun },
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun .name = "filesystem",
170*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
171*4882a593Smuzhiyun .size = MTDPART_SIZ_FULL,
172*4882a593Smuzhiyun .mask_flags = 0,
173*4882a593Smuzhiyun },
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun static struct physmap_flash_data da850_evm_norflash_data = {
177*4882a593Smuzhiyun .width = 2,
178*4882a593Smuzhiyun .parts = da850_evm_norflash_partition,
179*4882a593Smuzhiyun .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition),
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun static struct resource da850_evm_norflash_resource[] = {
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun .start = DA8XX_AEMIF_CS2_BASE,
185*4882a593Smuzhiyun .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1,
186*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
187*4882a593Smuzhiyun },
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
191*4882a593Smuzhiyun * (128K blocks). It may be used instead of the (default) SPI flash
192*4882a593Smuzhiyun * to boot, using TI's tools to install the secondary boot loader
193*4882a593Smuzhiyun * (UBL) and U-Boot.
194*4882a593Smuzhiyun */
195*4882a593Smuzhiyun static struct mtd_partition da850_evm_nandflash_partition[] = {
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun .name = "u-boot env",
198*4882a593Smuzhiyun .offset = 0,
199*4882a593Smuzhiyun .size = SZ_128K,
200*4882a593Smuzhiyun .mask_flags = MTD_WRITEABLE,
201*4882a593Smuzhiyun },
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun .name = "UBL",
204*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
205*4882a593Smuzhiyun .size = SZ_128K,
206*4882a593Smuzhiyun .mask_flags = MTD_WRITEABLE,
207*4882a593Smuzhiyun },
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun .name = "u-boot",
210*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
211*4882a593Smuzhiyun .size = 4 * SZ_128K,
212*4882a593Smuzhiyun .mask_flags = MTD_WRITEABLE,
213*4882a593Smuzhiyun },
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun .name = "kernel",
216*4882a593Smuzhiyun .offset = 0x200000,
217*4882a593Smuzhiyun .size = SZ_2M,
218*4882a593Smuzhiyun .mask_flags = 0,
219*4882a593Smuzhiyun },
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun .name = "filesystem",
222*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
223*4882a593Smuzhiyun .size = MTDPART_SIZ_FULL,
224*4882a593Smuzhiyun .mask_flags = 0,
225*4882a593Smuzhiyun },
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun static struct davinci_aemif_timing da850_evm_nandflash_timing = {
229*4882a593Smuzhiyun .wsetup = 24,
230*4882a593Smuzhiyun .wstrobe = 21,
231*4882a593Smuzhiyun .whold = 14,
232*4882a593Smuzhiyun .rsetup = 19,
233*4882a593Smuzhiyun .rstrobe = 50,
234*4882a593Smuzhiyun .rhold = 0,
235*4882a593Smuzhiyun .ta = 20,
236*4882a593Smuzhiyun };
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun static struct davinci_nand_pdata da850_evm_nandflash_data = {
239*4882a593Smuzhiyun .core_chipsel = 1,
240*4882a593Smuzhiyun .parts = da850_evm_nandflash_partition,
241*4882a593Smuzhiyun .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
242*4882a593Smuzhiyun .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
243*4882a593Smuzhiyun .ecc_bits = 4,
244*4882a593Smuzhiyun .bbt_options = NAND_BBT_USE_FLASH,
245*4882a593Smuzhiyun .timing = &da850_evm_nandflash_timing,
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun static struct resource da850_evm_nandflash_resource[] = {
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun .start = DA8XX_AEMIF_CS3_BASE,
251*4882a593Smuzhiyun .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
252*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
253*4882a593Smuzhiyun },
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun .start = DA8XX_AEMIF_CTL_BASE,
256*4882a593Smuzhiyun .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
257*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
258*4882a593Smuzhiyun },
259*4882a593Smuzhiyun };
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun static struct resource da850_evm_aemif_resource[] = {
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun .start = DA8XX_AEMIF_CTL_BASE,
264*4882a593Smuzhiyun .end = DA8XX_AEMIF_CTL_BASE + SZ_32K,
265*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun };
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun .cs = 3,
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun static struct platform_device da850_evm_aemif_devices[] = {
276*4882a593Smuzhiyun {
277*4882a593Smuzhiyun .name = "davinci_nand",
278*4882a593Smuzhiyun .id = 1,
279*4882a593Smuzhiyun .dev = {
280*4882a593Smuzhiyun .platform_data = &da850_evm_nandflash_data,
281*4882a593Smuzhiyun },
282*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource),
283*4882a593Smuzhiyun .resource = da850_evm_nandflash_resource,
284*4882a593Smuzhiyun },
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun .name = "physmap-flash",
287*4882a593Smuzhiyun .id = 0,
288*4882a593Smuzhiyun .dev = {
289*4882a593Smuzhiyun .platform_data = &da850_evm_norflash_data,
290*4882a593Smuzhiyun },
291*4882a593Smuzhiyun .num_resources = 1,
292*4882a593Smuzhiyun .resource = da850_evm_norflash_resource,
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun };
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun static struct aemif_platform_data da850_evm_aemif_pdata = {
297*4882a593Smuzhiyun .cs_offset = 2,
298*4882a593Smuzhiyun .abus_data = da850_evm_aemif_abus_data,
299*4882a593Smuzhiyun .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data),
300*4882a593Smuzhiyun .sub_devices = da850_evm_aemif_devices,
301*4882a593Smuzhiyun .num_sub_devices = ARRAY_SIZE(da850_evm_aemif_devices),
302*4882a593Smuzhiyun };
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun static struct platform_device da850_evm_aemif_device = {
305*4882a593Smuzhiyun .name = "ti-aemif",
306*4882a593Smuzhiyun .id = -1,
307*4882a593Smuzhiyun .dev = {
308*4882a593Smuzhiyun .platform_data = &da850_evm_aemif_pdata,
309*4882a593Smuzhiyun },
310*4882a593Smuzhiyun .resource = da850_evm_aemif_resource,
311*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(da850_evm_aemif_resource),
312*4882a593Smuzhiyun };
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun static const short da850_evm_nand_pins[] = {
315*4882a593Smuzhiyun DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
316*4882a593Smuzhiyun DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
317*4882a593Smuzhiyun DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
318*4882a593Smuzhiyun DA850_NEMA_WE, DA850_NEMA_OE,
319*4882a593Smuzhiyun -1
320*4882a593Smuzhiyun };
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun static const short da850_evm_nor_pins[] = {
323*4882a593Smuzhiyun DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
324*4882a593Smuzhiyun DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
325*4882a593Smuzhiyun DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
326*4882a593Smuzhiyun DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
327*4882a593Smuzhiyun DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
328*4882a593Smuzhiyun DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
329*4882a593Smuzhiyun DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
330*4882a593Smuzhiyun DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
331*4882a593Smuzhiyun DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
332*4882a593Smuzhiyun DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
333*4882a593Smuzhiyun DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
334*4882a593Smuzhiyun DA850_EMA_A_22, DA850_EMA_A_23,
335*4882a593Smuzhiyun -1
336*4882a593Smuzhiyun };
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun #define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI)
339*4882a593Smuzhiyun
da850_evm_setup_nor_nand(void)340*4882a593Smuzhiyun static inline void da850_evm_setup_nor_nand(void)
341*4882a593Smuzhiyun {
342*4882a593Smuzhiyun int ret = 0;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun if (!HAS_MMC) {
345*4882a593Smuzhiyun ret = davinci_cfg_reg_list(da850_evm_nand_pins);
346*4882a593Smuzhiyun if (ret)
347*4882a593Smuzhiyun pr_warn("%s: NAND mux setup failed: %d\n",
348*4882a593Smuzhiyun __func__, ret);
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun ret = davinci_cfg_reg_list(da850_evm_nor_pins);
351*4882a593Smuzhiyun if (ret)
352*4882a593Smuzhiyun pr_warn("%s: NOR mux setup failed: %d\n",
353*4882a593Smuzhiyun __func__, ret);
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun ret = platform_device_register(&da850_evm_aemif_device);
356*4882a593Smuzhiyun if (ret)
357*4882a593Smuzhiyun pr_warn("%s: registering aemif failed: %d\n",
358*4882a593Smuzhiyun __func__, ret);
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun #ifdef CONFIG_DA850_UI_RMII
da850_evm_setup_emac_rmii(int rmii_sel)363*4882a593Smuzhiyun static inline void da850_evm_setup_emac_rmii(int rmii_sel)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun struct davinci_soc_info *soc_info = &davinci_soc_info;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun soc_info->emac_pdata->rmii_en = 1;
368*4882a593Smuzhiyun gpio_set_value_cansleep(rmii_sel, 0);
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun #else
da850_evm_setup_emac_rmii(int rmii_sel)371*4882a593Smuzhiyun static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
372*4882a593Smuzhiyun #endif
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun #define DA850_KEYS_DEBOUNCE_MS 10
376*4882a593Smuzhiyun /*
377*4882a593Smuzhiyun * At 200ms polling interval it is possible to miss an
378*4882a593Smuzhiyun * event by tapping very lightly on the push button but most
379*4882a593Smuzhiyun * pushes do result in an event; longer intervals require the
380*4882a593Smuzhiyun * user to hold the button whereas shorter intervals require
381*4882a593Smuzhiyun * more CPU time for polling.
382*4882a593Smuzhiyun */
383*4882a593Smuzhiyun #define DA850_GPIO_KEYS_POLL_MS 200
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun enum da850_evm_ui_exp_pins {
386*4882a593Smuzhiyun DA850_EVM_UI_EXP_SEL_C = 5,
387*4882a593Smuzhiyun DA850_EVM_UI_EXP_SEL_B,
388*4882a593Smuzhiyun DA850_EVM_UI_EXP_SEL_A,
389*4882a593Smuzhiyun DA850_EVM_UI_EXP_PB8,
390*4882a593Smuzhiyun DA850_EVM_UI_EXP_PB7,
391*4882a593Smuzhiyun DA850_EVM_UI_EXP_PB6,
392*4882a593Smuzhiyun DA850_EVM_UI_EXP_PB5,
393*4882a593Smuzhiyun DA850_EVM_UI_EXP_PB4,
394*4882a593Smuzhiyun DA850_EVM_UI_EXP_PB3,
395*4882a593Smuzhiyun DA850_EVM_UI_EXP_PB2,
396*4882a593Smuzhiyun DA850_EVM_UI_EXP_PB1,
397*4882a593Smuzhiyun };
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun static const char * const da850_evm_ui_exp[] = {
400*4882a593Smuzhiyun [DA850_EVM_UI_EXP_SEL_C] = "sel_c",
401*4882a593Smuzhiyun [DA850_EVM_UI_EXP_SEL_B] = "sel_b",
402*4882a593Smuzhiyun [DA850_EVM_UI_EXP_SEL_A] = "sel_a",
403*4882a593Smuzhiyun [DA850_EVM_UI_EXP_PB8] = "pb8",
404*4882a593Smuzhiyun [DA850_EVM_UI_EXP_PB7] = "pb7",
405*4882a593Smuzhiyun [DA850_EVM_UI_EXP_PB6] = "pb6",
406*4882a593Smuzhiyun [DA850_EVM_UI_EXP_PB5] = "pb5",
407*4882a593Smuzhiyun [DA850_EVM_UI_EXP_PB4] = "pb4",
408*4882a593Smuzhiyun [DA850_EVM_UI_EXP_PB3] = "pb3",
409*4882a593Smuzhiyun [DA850_EVM_UI_EXP_PB2] = "pb2",
410*4882a593Smuzhiyun [DA850_EVM_UI_EXP_PB1] = "pb1",
411*4882a593Smuzhiyun };
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun #define DA850_N_UI_PB 8
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun static struct gpio_keys_button da850_evm_ui_keys[] = {
416*4882a593Smuzhiyun [0 ... DA850_N_UI_PB - 1] = {
417*4882a593Smuzhiyun .type = EV_KEY,
418*4882a593Smuzhiyun .active_low = 1,
419*4882a593Smuzhiyun .wakeup = 0,
420*4882a593Smuzhiyun .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
421*4882a593Smuzhiyun .code = -1, /* assigned at runtime */
422*4882a593Smuzhiyun .gpio = -1, /* assigned at runtime */
423*4882a593Smuzhiyun .desc = NULL, /* assigned at runtime */
424*4882a593Smuzhiyun },
425*4882a593Smuzhiyun };
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = {
428*4882a593Smuzhiyun .buttons = da850_evm_ui_keys,
429*4882a593Smuzhiyun .nbuttons = ARRAY_SIZE(da850_evm_ui_keys),
430*4882a593Smuzhiyun .poll_interval = DA850_GPIO_KEYS_POLL_MS,
431*4882a593Smuzhiyun };
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun static struct platform_device da850_evm_ui_keys_device = {
434*4882a593Smuzhiyun .name = "gpio-keys-polled",
435*4882a593Smuzhiyun .id = 0,
436*4882a593Smuzhiyun .dev = {
437*4882a593Smuzhiyun .platform_data = &da850_evm_ui_keys_pdata
438*4882a593Smuzhiyun },
439*4882a593Smuzhiyun };
440*4882a593Smuzhiyun
da850_evm_ui_keys_init(unsigned gpio)441*4882a593Smuzhiyun static void da850_evm_ui_keys_init(unsigned gpio)
442*4882a593Smuzhiyun {
443*4882a593Smuzhiyun int i;
444*4882a593Smuzhiyun struct gpio_keys_button *button;
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun for (i = 0; i < DA850_N_UI_PB; i++) {
447*4882a593Smuzhiyun button = &da850_evm_ui_keys[i];
448*4882a593Smuzhiyun button->code = KEY_F8 - i;
449*4882a593Smuzhiyun button->desc = da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i];
450*4882a593Smuzhiyun button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun #ifdef CONFIG_DA850_UI_SD_VIDEO_PORT
da850_evm_setup_video_port(int video_sel)455*4882a593Smuzhiyun static inline void da850_evm_setup_video_port(int video_sel)
456*4882a593Smuzhiyun {
457*4882a593Smuzhiyun gpio_set_value_cansleep(video_sel, 0);
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun #else
da850_evm_setup_video_port(int video_sel)460*4882a593Smuzhiyun static inline void da850_evm_setup_video_port(int video_sel) { }
461*4882a593Smuzhiyun #endif
462*4882a593Smuzhiyun
da850_evm_ui_expander_setup(struct i2c_client * client,unsigned gpio,unsigned ngpio,void * c)463*4882a593Smuzhiyun static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
464*4882a593Smuzhiyun unsigned ngpio, void *c)
465*4882a593Smuzhiyun {
466*4882a593Smuzhiyun int sel_a, sel_b, sel_c, ret;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun sel_a = gpio + DA850_EVM_UI_EXP_SEL_A;
469*4882a593Smuzhiyun sel_b = gpio + DA850_EVM_UI_EXP_SEL_B;
470*4882a593Smuzhiyun sel_c = gpio + DA850_EVM_UI_EXP_SEL_C;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]);
473*4882a593Smuzhiyun if (ret) {
474*4882a593Smuzhiyun pr_warn("Cannot open UI expander pin %d\n", sel_a);
475*4882a593Smuzhiyun goto exp_setup_sela_fail;
476*4882a593Smuzhiyun }
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]);
479*4882a593Smuzhiyun if (ret) {
480*4882a593Smuzhiyun pr_warn("Cannot open UI expander pin %d\n", sel_b);
481*4882a593Smuzhiyun goto exp_setup_selb_fail;
482*4882a593Smuzhiyun }
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]);
485*4882a593Smuzhiyun if (ret) {
486*4882a593Smuzhiyun pr_warn("Cannot open UI expander pin %d\n", sel_c);
487*4882a593Smuzhiyun goto exp_setup_selc_fail;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun /* deselect all functionalities */
491*4882a593Smuzhiyun gpio_direction_output(sel_a, 1);
492*4882a593Smuzhiyun gpio_direction_output(sel_b, 1);
493*4882a593Smuzhiyun gpio_direction_output(sel_c, 1);
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun da850_evm_ui_keys_init(gpio);
496*4882a593Smuzhiyun ret = platform_device_register(&da850_evm_ui_keys_device);
497*4882a593Smuzhiyun if (ret) {
498*4882a593Smuzhiyun pr_warn("Could not register UI GPIO expander push-buttons");
499*4882a593Smuzhiyun goto exp_setup_keys_fail;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun pr_info("DA850/OMAP-L138 EVM UI card detected\n");
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun da850_evm_setup_nor_nand();
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun da850_evm_setup_emac_rmii(sel_a);
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun da850_evm_setup_video_port(sel_c);
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun return 0;
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun exp_setup_keys_fail:
513*4882a593Smuzhiyun gpio_free(sel_c);
514*4882a593Smuzhiyun exp_setup_selc_fail:
515*4882a593Smuzhiyun gpio_free(sel_b);
516*4882a593Smuzhiyun exp_setup_selb_fail:
517*4882a593Smuzhiyun gpio_free(sel_a);
518*4882a593Smuzhiyun exp_setup_sela_fail:
519*4882a593Smuzhiyun return ret;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun
da850_evm_ui_expander_teardown(struct i2c_client * client,unsigned gpio,unsigned ngpio,void * c)522*4882a593Smuzhiyun static int da850_evm_ui_expander_teardown(struct i2c_client *client,
523*4882a593Smuzhiyun unsigned gpio, unsigned ngpio, void *c)
524*4882a593Smuzhiyun {
525*4882a593Smuzhiyun platform_device_unregister(&da850_evm_ui_keys_device);
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun /* deselect all functionalities */
528*4882a593Smuzhiyun gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1);
529*4882a593Smuzhiyun gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1);
530*4882a593Smuzhiyun gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1);
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C);
533*4882a593Smuzhiyun gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B);
534*4882a593Smuzhiyun gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A);
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun return 0;
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun /* assign the baseboard expander's GPIOs after the UI board's */
540*4882a593Smuzhiyun #define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp)
541*4882a593Smuzhiyun #define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS)
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun enum da850_evm_bb_exp_pins {
544*4882a593Smuzhiyun DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0,
545*4882a593Smuzhiyun DA850_EVM_BB_EXP_SW_RST,
546*4882a593Smuzhiyun DA850_EVM_BB_EXP_TP_23,
547*4882a593Smuzhiyun DA850_EVM_BB_EXP_TP_22,
548*4882a593Smuzhiyun DA850_EVM_BB_EXP_TP_21,
549*4882a593Smuzhiyun DA850_EVM_BB_EXP_USER_PB1,
550*4882a593Smuzhiyun DA850_EVM_BB_EXP_USER_LED2,
551*4882a593Smuzhiyun DA850_EVM_BB_EXP_USER_LED1,
552*4882a593Smuzhiyun DA850_EVM_BB_EXP_USER_SW1,
553*4882a593Smuzhiyun DA850_EVM_BB_EXP_USER_SW2,
554*4882a593Smuzhiyun DA850_EVM_BB_EXP_USER_SW3,
555*4882a593Smuzhiyun DA850_EVM_BB_EXP_USER_SW4,
556*4882a593Smuzhiyun DA850_EVM_BB_EXP_USER_SW5,
557*4882a593Smuzhiyun DA850_EVM_BB_EXP_USER_SW6,
558*4882a593Smuzhiyun DA850_EVM_BB_EXP_USER_SW7,
559*4882a593Smuzhiyun DA850_EVM_BB_EXP_USER_SW8
560*4882a593Smuzhiyun };
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun static const char * const da850_evm_bb_exp[] = {
563*4882a593Smuzhiyun [DA850_EVM_BB_EXP_DEEP_SLEEP_EN] = "deep_sleep_en",
564*4882a593Smuzhiyun [DA850_EVM_BB_EXP_SW_RST] = "sw_rst",
565*4882a593Smuzhiyun [DA850_EVM_BB_EXP_TP_23] = "tp_23",
566*4882a593Smuzhiyun [DA850_EVM_BB_EXP_TP_22] = "tp_22",
567*4882a593Smuzhiyun [DA850_EVM_BB_EXP_TP_21] = "tp_21",
568*4882a593Smuzhiyun [DA850_EVM_BB_EXP_USER_PB1] = "user_pb1",
569*4882a593Smuzhiyun [DA850_EVM_BB_EXP_USER_LED2] = "user_led2",
570*4882a593Smuzhiyun [DA850_EVM_BB_EXP_USER_LED1] = "user_led1",
571*4882a593Smuzhiyun [DA850_EVM_BB_EXP_USER_SW1] = "user_sw1",
572*4882a593Smuzhiyun [DA850_EVM_BB_EXP_USER_SW2] = "user_sw2",
573*4882a593Smuzhiyun [DA850_EVM_BB_EXP_USER_SW3] = "user_sw3",
574*4882a593Smuzhiyun [DA850_EVM_BB_EXP_USER_SW4] = "user_sw4",
575*4882a593Smuzhiyun [DA850_EVM_BB_EXP_USER_SW5] = "user_sw5",
576*4882a593Smuzhiyun [DA850_EVM_BB_EXP_USER_SW6] = "user_sw6",
577*4882a593Smuzhiyun [DA850_EVM_BB_EXP_USER_SW7] = "user_sw7",
578*4882a593Smuzhiyun [DA850_EVM_BB_EXP_USER_SW8] = "user_sw8",
579*4882a593Smuzhiyun };
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun #define DA850_N_BB_USER_SW 8
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun static struct gpio_keys_button da850_evm_bb_keys[] = {
584*4882a593Smuzhiyun [0] = {
585*4882a593Smuzhiyun .type = EV_KEY,
586*4882a593Smuzhiyun .active_low = 1,
587*4882a593Smuzhiyun .wakeup = 0,
588*4882a593Smuzhiyun .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
589*4882a593Smuzhiyun .code = KEY_PROG1,
590*4882a593Smuzhiyun .desc = NULL, /* assigned at runtime */
591*4882a593Smuzhiyun .gpio = -1, /* assigned at runtime */
592*4882a593Smuzhiyun },
593*4882a593Smuzhiyun [1 ... DA850_N_BB_USER_SW] = {
594*4882a593Smuzhiyun .type = EV_SW,
595*4882a593Smuzhiyun .active_low = 1,
596*4882a593Smuzhiyun .wakeup = 0,
597*4882a593Smuzhiyun .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
598*4882a593Smuzhiyun .code = -1, /* assigned at runtime */
599*4882a593Smuzhiyun .desc = NULL, /* assigned at runtime */
600*4882a593Smuzhiyun .gpio = -1, /* assigned at runtime */
601*4882a593Smuzhiyun },
602*4882a593Smuzhiyun };
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = {
605*4882a593Smuzhiyun .buttons = da850_evm_bb_keys,
606*4882a593Smuzhiyun .nbuttons = ARRAY_SIZE(da850_evm_bb_keys),
607*4882a593Smuzhiyun .poll_interval = DA850_GPIO_KEYS_POLL_MS,
608*4882a593Smuzhiyun };
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun static struct platform_device da850_evm_bb_keys_device = {
611*4882a593Smuzhiyun .name = "gpio-keys-polled",
612*4882a593Smuzhiyun .id = 1,
613*4882a593Smuzhiyun .dev = {
614*4882a593Smuzhiyun .platform_data = &da850_evm_bb_keys_pdata
615*4882a593Smuzhiyun },
616*4882a593Smuzhiyun };
617*4882a593Smuzhiyun
da850_evm_bb_keys_init(unsigned gpio)618*4882a593Smuzhiyun static void da850_evm_bb_keys_init(unsigned gpio)
619*4882a593Smuzhiyun {
620*4882a593Smuzhiyun int i;
621*4882a593Smuzhiyun struct gpio_keys_button *button;
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun button = &da850_evm_bb_keys[0];
624*4882a593Smuzhiyun button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1];
625*4882a593Smuzhiyun button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun for (i = 0; i < DA850_N_BB_USER_SW; i++) {
628*4882a593Smuzhiyun button = &da850_evm_bb_keys[i + 1];
629*4882a593Smuzhiyun button->code = SW_LID + i;
630*4882a593Smuzhiyun button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i];
631*4882a593Smuzhiyun button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun }
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun static struct gpio_led da850_evm_bb_leds[] = {
636*4882a593Smuzhiyun {
637*4882a593Smuzhiyun .name = "user_led2",
638*4882a593Smuzhiyun },
639*4882a593Smuzhiyun {
640*4882a593Smuzhiyun .name = "user_led1",
641*4882a593Smuzhiyun },
642*4882a593Smuzhiyun };
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun static struct gpio_led_platform_data da850_evm_bb_leds_pdata = {
645*4882a593Smuzhiyun .leds = da850_evm_bb_leds,
646*4882a593Smuzhiyun .num_leds = ARRAY_SIZE(da850_evm_bb_leds),
647*4882a593Smuzhiyun };
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun static struct gpiod_lookup_table da850_evm_bb_leds_gpio_table = {
650*4882a593Smuzhiyun .dev_id = "leds-gpio",
651*4882a593Smuzhiyun .table = {
652*4882a593Smuzhiyun GPIO_LOOKUP_IDX("i2c-bb-expander",
653*4882a593Smuzhiyun DA850_EVM_BB_EXP_USER_LED2, NULL,
654*4882a593Smuzhiyun 0, GPIO_ACTIVE_LOW),
655*4882a593Smuzhiyun GPIO_LOOKUP_IDX("i2c-bb-expander",
656*4882a593Smuzhiyun DA850_EVM_BB_EXP_USER_LED2 + 1, NULL,
657*4882a593Smuzhiyun 1, GPIO_ACTIVE_LOW),
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun { },
660*4882a593Smuzhiyun },
661*4882a593Smuzhiyun };
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun static struct platform_device da850_evm_bb_leds_device = {
664*4882a593Smuzhiyun .name = "leds-gpio",
665*4882a593Smuzhiyun .id = -1,
666*4882a593Smuzhiyun .dev = {
667*4882a593Smuzhiyun .platform_data = &da850_evm_bb_leds_pdata
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun };
670*4882a593Smuzhiyun
da850_evm_bb_expander_setup(struct i2c_client * client,unsigned gpio,unsigned ngpio,void * c)671*4882a593Smuzhiyun static int da850_evm_bb_expander_setup(struct i2c_client *client,
672*4882a593Smuzhiyun unsigned gpio, unsigned ngpio,
673*4882a593Smuzhiyun void *c)
674*4882a593Smuzhiyun {
675*4882a593Smuzhiyun int ret;
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun /*
678*4882a593Smuzhiyun * Register the switches and pushbutton on the baseboard as a gpio-keys
679*4882a593Smuzhiyun * device.
680*4882a593Smuzhiyun */
681*4882a593Smuzhiyun da850_evm_bb_keys_init(gpio);
682*4882a593Smuzhiyun ret = platform_device_register(&da850_evm_bb_keys_device);
683*4882a593Smuzhiyun if (ret) {
684*4882a593Smuzhiyun pr_warn("Could not register baseboard GPIO expander keys");
685*4882a593Smuzhiyun goto io_exp_setup_sw_fail;
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun gpiod_add_lookup_table(&da850_evm_bb_leds_gpio_table);
689*4882a593Smuzhiyun ret = platform_device_register(&da850_evm_bb_leds_device);
690*4882a593Smuzhiyun if (ret) {
691*4882a593Smuzhiyun pr_warn("Could not register baseboard GPIO expander LEDs");
692*4882a593Smuzhiyun goto io_exp_setup_leds_fail;
693*4882a593Smuzhiyun }
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun return 0;
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun io_exp_setup_leds_fail:
698*4882a593Smuzhiyun platform_device_unregister(&da850_evm_bb_keys_device);
699*4882a593Smuzhiyun io_exp_setup_sw_fail:
700*4882a593Smuzhiyun return ret;
701*4882a593Smuzhiyun }
702*4882a593Smuzhiyun
da850_evm_bb_expander_teardown(struct i2c_client * client,unsigned gpio,unsigned ngpio,void * c)703*4882a593Smuzhiyun static int da850_evm_bb_expander_teardown(struct i2c_client *client,
704*4882a593Smuzhiyun unsigned gpio, unsigned ngpio, void *c)
705*4882a593Smuzhiyun {
706*4882a593Smuzhiyun platform_device_unregister(&da850_evm_bb_leds_device);
707*4882a593Smuzhiyun platform_device_unregister(&da850_evm_bb_keys_device);
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun return 0;
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun static struct pca953x_platform_data da850_evm_ui_expander_info = {
713*4882a593Smuzhiyun .gpio_base = DAVINCI_N_GPIO,
714*4882a593Smuzhiyun .setup = da850_evm_ui_expander_setup,
715*4882a593Smuzhiyun .teardown = da850_evm_ui_expander_teardown,
716*4882a593Smuzhiyun .names = da850_evm_ui_exp,
717*4882a593Smuzhiyun };
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun static struct pca953x_platform_data da850_evm_bb_expander_info = {
720*4882a593Smuzhiyun .gpio_base = DA850_BB_EXPANDER_GPIO_BASE,
721*4882a593Smuzhiyun .setup = da850_evm_bb_expander_setup,
722*4882a593Smuzhiyun .teardown = da850_evm_bb_expander_teardown,
723*4882a593Smuzhiyun .names = da850_evm_bb_exp,
724*4882a593Smuzhiyun };
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
727*4882a593Smuzhiyun {
728*4882a593Smuzhiyun I2C_BOARD_INFO("tlv320aic3x", 0x18),
729*4882a593Smuzhiyun },
730*4882a593Smuzhiyun {
731*4882a593Smuzhiyun I2C_BOARD_INFO("tca6416", 0x20),
732*4882a593Smuzhiyun .dev_name = "ui-expander",
733*4882a593Smuzhiyun .platform_data = &da850_evm_ui_expander_info,
734*4882a593Smuzhiyun },
735*4882a593Smuzhiyun {
736*4882a593Smuzhiyun I2C_BOARD_INFO("tca6416", 0x21),
737*4882a593Smuzhiyun .dev_name = "bb-expander",
738*4882a593Smuzhiyun .platform_data = &da850_evm_bb_expander_info,
739*4882a593Smuzhiyun },
740*4882a593Smuzhiyun };
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
743*4882a593Smuzhiyun .bus_freq = 100, /* kHz */
744*4882a593Smuzhiyun .bus_delay = 0, /* usec */
745*4882a593Smuzhiyun };
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun /* davinci da850 evm audio machine driver */
748*4882a593Smuzhiyun static u8 da850_iis_serializer_direction[] = {
749*4882a593Smuzhiyun INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
750*4882a593Smuzhiyun INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
751*4882a593Smuzhiyun INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE,
752*4882a593Smuzhiyun RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
753*4882a593Smuzhiyun };
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun static struct snd_platform_data da850_evm_snd_data = {
756*4882a593Smuzhiyun .tx_dma_offset = 0x2000,
757*4882a593Smuzhiyun .rx_dma_offset = 0x2000,
758*4882a593Smuzhiyun .op_mode = DAVINCI_MCASP_IIS_MODE,
759*4882a593Smuzhiyun .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction),
760*4882a593Smuzhiyun .tdm_slots = 2,
761*4882a593Smuzhiyun .serial_dir = da850_iis_serializer_direction,
762*4882a593Smuzhiyun .asp_chan_q = EVENTQ_0,
763*4882a593Smuzhiyun .ram_chan_q = EVENTQ_1,
764*4882a593Smuzhiyun .version = MCASP_VERSION_2,
765*4882a593Smuzhiyun .txnumevt = 1,
766*4882a593Smuzhiyun .rxnumevt = 1,
767*4882a593Smuzhiyun .sram_size_playback = SZ_8K,
768*4882a593Smuzhiyun .sram_size_capture = SZ_8K,
769*4882a593Smuzhiyun };
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun static const short da850_evm_mcasp_pins[] __initconst = {
772*4882a593Smuzhiyun DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
773*4882a593Smuzhiyun DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
774*4882a593Smuzhiyun DA850_AXR_11, DA850_AXR_12,
775*4882a593Smuzhiyun -1
776*4882a593Smuzhiyun };
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun #define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
779*4882a593Smuzhiyun #define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun static struct gpiod_lookup_table mmc_gpios_table = {
782*4882a593Smuzhiyun .dev_id = "da830-mmc.0",
783*4882a593Smuzhiyun .table = {
784*4882a593Smuzhiyun /* gpio chip 2 contains gpio range 64-95 */
785*4882a593Smuzhiyun GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_CD_PIN, "cd",
786*4882a593Smuzhiyun GPIO_ACTIVE_LOW),
787*4882a593Smuzhiyun GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_WP_PIN, "wp",
788*4882a593Smuzhiyun GPIO_ACTIVE_HIGH),
789*4882a593Smuzhiyun { }
790*4882a593Smuzhiyun },
791*4882a593Smuzhiyun };
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun static struct davinci_mmc_config da850_mmc_config = {
794*4882a593Smuzhiyun .wires = 4,
795*4882a593Smuzhiyun .max_freq = 50000000,
796*4882a593Smuzhiyun .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
797*4882a593Smuzhiyun };
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun static const short da850_evm_mmcsd0_pins[] __initconst = {
800*4882a593Smuzhiyun DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
801*4882a593Smuzhiyun DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
802*4882a593Smuzhiyun DA850_GPIO4_0, DA850_GPIO4_1,
803*4882a593Smuzhiyun -1
804*4882a593Smuzhiyun };
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun static struct property_entry da850_lcd_backlight_props[] = {
807*4882a593Smuzhiyun PROPERTY_ENTRY_BOOL("default-on"),
808*4882a593Smuzhiyun { }
809*4882a593Smuzhiyun };
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun static struct gpiod_lookup_table da850_lcd_backlight_gpio_table = {
812*4882a593Smuzhiyun .dev_id = "gpio-backlight",
813*4882a593Smuzhiyun .table = {
814*4882a593Smuzhiyun GPIO_LOOKUP("davinci_gpio", DA850_LCD_BL_PIN, NULL, 0),
815*4882a593Smuzhiyun { }
816*4882a593Smuzhiyun },
817*4882a593Smuzhiyun };
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun static const struct platform_device_info da850_lcd_backlight_info = {
820*4882a593Smuzhiyun .name = "gpio-backlight",
821*4882a593Smuzhiyun .id = PLATFORM_DEVID_NONE,
822*4882a593Smuzhiyun .properties = da850_lcd_backlight_props,
823*4882a593Smuzhiyun };
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun static struct regulator_consumer_supply da850_lcd_supplies[] = {
826*4882a593Smuzhiyun REGULATOR_SUPPLY("lcd", NULL),
827*4882a593Smuzhiyun };
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun static struct regulator_init_data da850_lcd_supply_data = {
830*4882a593Smuzhiyun .consumer_supplies = da850_lcd_supplies,
831*4882a593Smuzhiyun .num_consumer_supplies = ARRAY_SIZE(da850_lcd_supplies),
832*4882a593Smuzhiyun .constraints = {
833*4882a593Smuzhiyun .valid_ops_mask = REGULATOR_CHANGE_STATUS,
834*4882a593Smuzhiyun },
835*4882a593Smuzhiyun };
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun static struct fixed_voltage_config da850_lcd_supply = {
838*4882a593Smuzhiyun .supply_name = "lcd",
839*4882a593Smuzhiyun .microvolts = 33000000,
840*4882a593Smuzhiyun .init_data = &da850_lcd_supply_data,
841*4882a593Smuzhiyun };
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun static struct platform_device da850_lcd_supply_device = {
844*4882a593Smuzhiyun .name = "reg-fixed-voltage",
845*4882a593Smuzhiyun .id = 1, /* Dummy fixed regulator is 0 */
846*4882a593Smuzhiyun .dev = {
847*4882a593Smuzhiyun .platform_data = &da850_lcd_supply,
848*4882a593Smuzhiyun },
849*4882a593Smuzhiyun };
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun static struct gpiod_lookup_table da850_lcd_supply_gpio_table = {
852*4882a593Smuzhiyun .dev_id = "reg-fixed-voltage.1",
853*4882a593Smuzhiyun .table = {
854*4882a593Smuzhiyun GPIO_LOOKUP("davinci_gpio", DA850_LCD_PWR_PIN, NULL, 0),
855*4882a593Smuzhiyun { }
856*4882a593Smuzhiyun },
857*4882a593Smuzhiyun };
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun static struct gpiod_lookup_table *da850_lcd_gpio_lookups[] = {
860*4882a593Smuzhiyun &da850_lcd_backlight_gpio_table,
861*4882a593Smuzhiyun &da850_lcd_supply_gpio_table,
862*4882a593Smuzhiyun };
863*4882a593Smuzhiyun
da850_lcd_hw_init(void)864*4882a593Smuzhiyun static int da850_lcd_hw_init(void)
865*4882a593Smuzhiyun {
866*4882a593Smuzhiyun struct platform_device *backlight;
867*4882a593Smuzhiyun int status;
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun gpiod_add_lookup_tables(da850_lcd_gpio_lookups,
870*4882a593Smuzhiyun ARRAY_SIZE(da850_lcd_gpio_lookups));
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun backlight = platform_device_register_full(&da850_lcd_backlight_info);
873*4882a593Smuzhiyun if (IS_ERR(backlight))
874*4882a593Smuzhiyun return PTR_ERR(backlight);
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun status = platform_device_register(&da850_lcd_supply_device);
877*4882a593Smuzhiyun if (status)
878*4882a593Smuzhiyun return status;
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun return 0;
881*4882a593Smuzhiyun }
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun /* Fixed regulator support */
884*4882a593Smuzhiyun static struct regulator_consumer_supply fixed_supplies[] = {
885*4882a593Smuzhiyun /* Baseboard 3.3V: 5V -> TPS73701DCQ -> 3.3V */
886*4882a593Smuzhiyun REGULATOR_SUPPLY("AVDD", "1-0018"),
887*4882a593Smuzhiyun REGULATOR_SUPPLY("DRVDD", "1-0018"),
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun /* Baseboard 1.8V: 5V -> TPS73701DCQ -> 1.8V */
890*4882a593Smuzhiyun REGULATOR_SUPPLY("DVDD", "1-0018"),
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun /* UI card 3.3V: 5V -> TPS73701DCQ -> 3.3V */
893*4882a593Smuzhiyun REGULATOR_SUPPLY("vcc", "1-0020"),
894*4882a593Smuzhiyun };
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun /* TPS65070 voltage regulator support */
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun /* 3.3V */
899*4882a593Smuzhiyun static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
900*4882a593Smuzhiyun {
901*4882a593Smuzhiyun .supply = "usb0_vdda33",
902*4882a593Smuzhiyun },
903*4882a593Smuzhiyun {
904*4882a593Smuzhiyun .supply = "usb1_vdda33",
905*4882a593Smuzhiyun },
906*4882a593Smuzhiyun };
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun /* 3.3V or 1.8V */
909*4882a593Smuzhiyun static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
910*4882a593Smuzhiyun {
911*4882a593Smuzhiyun .supply = "dvdd3318_a",
912*4882a593Smuzhiyun },
913*4882a593Smuzhiyun {
914*4882a593Smuzhiyun .supply = "dvdd3318_b",
915*4882a593Smuzhiyun },
916*4882a593Smuzhiyun {
917*4882a593Smuzhiyun .supply = "dvdd3318_c",
918*4882a593Smuzhiyun },
919*4882a593Smuzhiyun REGULATOR_SUPPLY("IOVDD", "1-0018"),
920*4882a593Smuzhiyun };
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun /* 1.2V */
923*4882a593Smuzhiyun static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
924*4882a593Smuzhiyun {
925*4882a593Smuzhiyun .supply = "cvdd",
926*4882a593Smuzhiyun },
927*4882a593Smuzhiyun };
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun /* 1.8V LDO */
930*4882a593Smuzhiyun static struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
931*4882a593Smuzhiyun {
932*4882a593Smuzhiyun .supply = "sata_vddr",
933*4882a593Smuzhiyun },
934*4882a593Smuzhiyun {
935*4882a593Smuzhiyun .supply = "usb0_vdda18",
936*4882a593Smuzhiyun },
937*4882a593Smuzhiyun {
938*4882a593Smuzhiyun .supply = "usb1_vdda18",
939*4882a593Smuzhiyun },
940*4882a593Smuzhiyun {
941*4882a593Smuzhiyun .supply = "ddr_dvdd18",
942*4882a593Smuzhiyun },
943*4882a593Smuzhiyun };
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun /* 1.2V LDO */
946*4882a593Smuzhiyun static struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
947*4882a593Smuzhiyun {
948*4882a593Smuzhiyun .supply = "sata_vdd",
949*4882a593Smuzhiyun },
950*4882a593Smuzhiyun {
951*4882a593Smuzhiyun .supply = "pll0_vdda",
952*4882a593Smuzhiyun },
953*4882a593Smuzhiyun {
954*4882a593Smuzhiyun .supply = "pll1_vdda",
955*4882a593Smuzhiyun },
956*4882a593Smuzhiyun {
957*4882a593Smuzhiyun .supply = "usbs_cvdd",
958*4882a593Smuzhiyun },
959*4882a593Smuzhiyun {
960*4882a593Smuzhiyun .supply = "vddarnwa1",
961*4882a593Smuzhiyun },
962*4882a593Smuzhiyun };
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun /* We take advantage of the fact that both defdcdc{2,3} are tied high */
965*4882a593Smuzhiyun static struct tps6507x_reg_platform_data tps6507x_platform_data = {
966*4882a593Smuzhiyun .defdcdc_default = true,
967*4882a593Smuzhiyun };
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun static struct regulator_init_data tps65070_regulator_data[] = {
970*4882a593Smuzhiyun /* dcdc1 */
971*4882a593Smuzhiyun {
972*4882a593Smuzhiyun .constraints = {
973*4882a593Smuzhiyun .min_uV = 3150000,
974*4882a593Smuzhiyun .max_uV = 3450000,
975*4882a593Smuzhiyun .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
976*4882a593Smuzhiyun REGULATOR_CHANGE_STATUS),
977*4882a593Smuzhiyun .boot_on = 1,
978*4882a593Smuzhiyun },
979*4882a593Smuzhiyun .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc1_consumers),
980*4882a593Smuzhiyun .consumer_supplies = tps65070_dcdc1_consumers,
981*4882a593Smuzhiyun },
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun /* dcdc2 */
984*4882a593Smuzhiyun {
985*4882a593Smuzhiyun .constraints = {
986*4882a593Smuzhiyun .min_uV = 1710000,
987*4882a593Smuzhiyun .max_uV = 3450000,
988*4882a593Smuzhiyun .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
989*4882a593Smuzhiyun REGULATOR_CHANGE_STATUS),
990*4882a593Smuzhiyun .boot_on = 1,
991*4882a593Smuzhiyun .always_on = 1,
992*4882a593Smuzhiyun },
993*4882a593Smuzhiyun .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
994*4882a593Smuzhiyun .consumer_supplies = tps65070_dcdc2_consumers,
995*4882a593Smuzhiyun .driver_data = &tps6507x_platform_data,
996*4882a593Smuzhiyun },
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun /* dcdc3 */
999*4882a593Smuzhiyun {
1000*4882a593Smuzhiyun .constraints = {
1001*4882a593Smuzhiyun .min_uV = 950000,
1002*4882a593Smuzhiyun .max_uV = 1350000,
1003*4882a593Smuzhiyun .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
1004*4882a593Smuzhiyun REGULATOR_CHANGE_STATUS),
1005*4882a593Smuzhiyun .boot_on = 1,
1006*4882a593Smuzhiyun },
1007*4882a593Smuzhiyun .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers),
1008*4882a593Smuzhiyun .consumer_supplies = tps65070_dcdc3_consumers,
1009*4882a593Smuzhiyun .driver_data = &tps6507x_platform_data,
1010*4882a593Smuzhiyun },
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun /* ldo1 */
1013*4882a593Smuzhiyun {
1014*4882a593Smuzhiyun .constraints = {
1015*4882a593Smuzhiyun .min_uV = 1710000,
1016*4882a593Smuzhiyun .max_uV = 1890000,
1017*4882a593Smuzhiyun .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
1018*4882a593Smuzhiyun REGULATOR_CHANGE_STATUS),
1019*4882a593Smuzhiyun .boot_on = 1,
1020*4882a593Smuzhiyun },
1021*4882a593Smuzhiyun .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo1_consumers),
1022*4882a593Smuzhiyun .consumer_supplies = tps65070_ldo1_consumers,
1023*4882a593Smuzhiyun },
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun /* ldo2 */
1026*4882a593Smuzhiyun {
1027*4882a593Smuzhiyun .constraints = {
1028*4882a593Smuzhiyun .min_uV = 1140000,
1029*4882a593Smuzhiyun .max_uV = 1320000,
1030*4882a593Smuzhiyun .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
1031*4882a593Smuzhiyun REGULATOR_CHANGE_STATUS),
1032*4882a593Smuzhiyun .boot_on = 1,
1033*4882a593Smuzhiyun },
1034*4882a593Smuzhiyun .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo2_consumers),
1035*4882a593Smuzhiyun .consumer_supplies = tps65070_ldo2_consumers,
1036*4882a593Smuzhiyun },
1037*4882a593Smuzhiyun };
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun static struct touchscreen_init_data tps6507x_touchscreen_data = {
1040*4882a593Smuzhiyun .poll_period = 30, /* ms between touch samples */
1041*4882a593Smuzhiyun .min_pressure = 0x30, /* minimum pressure to trigger touch */
1042*4882a593Smuzhiyun .vendor = 0, /* /sys/class/input/input?/id/vendor */
1043*4882a593Smuzhiyun .product = 65070, /* /sys/class/input/input?/id/product */
1044*4882a593Smuzhiyun .version = 0x100, /* /sys/class/input/input?/id/version */
1045*4882a593Smuzhiyun };
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun static struct tps6507x_board tps_board = {
1048*4882a593Smuzhiyun .tps6507x_pmic_init_data = &tps65070_regulator_data[0],
1049*4882a593Smuzhiyun .tps6507x_ts_init_data = &tps6507x_touchscreen_data,
1050*4882a593Smuzhiyun };
1051*4882a593Smuzhiyun
1052*4882a593Smuzhiyun static struct i2c_board_info __initdata da850_evm_tps65070_info[] = {
1053*4882a593Smuzhiyun {
1054*4882a593Smuzhiyun I2C_BOARD_INFO("tps6507x", 0x48),
1055*4882a593Smuzhiyun .platform_data = &tps_board,
1056*4882a593Smuzhiyun },
1057*4882a593Smuzhiyun };
1058*4882a593Smuzhiyun
pmic_tps65070_init(void)1059*4882a593Smuzhiyun static int __init pmic_tps65070_init(void)
1060*4882a593Smuzhiyun {
1061*4882a593Smuzhiyun return i2c_register_board_info(1, da850_evm_tps65070_info,
1062*4882a593Smuzhiyun ARRAY_SIZE(da850_evm_tps65070_info));
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun static const short da850_evm_lcdc_pins[] = {
1066*4882a593Smuzhiyun DA850_GPIO2_8, DA850_GPIO2_15,
1067*4882a593Smuzhiyun -1
1068*4882a593Smuzhiyun };
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun static const short da850_evm_mii_pins[] = {
1071*4882a593Smuzhiyun DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
1072*4882a593Smuzhiyun DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
1073*4882a593Smuzhiyun DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
1074*4882a593Smuzhiyun DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
1075*4882a593Smuzhiyun DA850_MDIO_D,
1076*4882a593Smuzhiyun -1
1077*4882a593Smuzhiyun };
1078*4882a593Smuzhiyun
1079*4882a593Smuzhiyun static const short da850_evm_rmii_pins[] = {
1080*4882a593Smuzhiyun DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
1081*4882a593Smuzhiyun DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
1082*4882a593Smuzhiyun DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
1083*4882a593Smuzhiyun DA850_MDIO_D,
1084*4882a593Smuzhiyun -1
1085*4882a593Smuzhiyun };
1086*4882a593Smuzhiyun
1087*4882a593Smuzhiyun static struct gpiod_hog da850_evm_emac_gpio_hogs[] = {
1088*4882a593Smuzhiyun {
1089*4882a593Smuzhiyun .chip_label = "davinci_gpio",
1090*4882a593Smuzhiyun .chip_hwnum = DA850_MII_MDIO_CLKEN_PIN,
1091*4882a593Smuzhiyun .line_name = "mdio_clk_en",
1092*4882a593Smuzhiyun .lflags = 0,
1093*4882a593Smuzhiyun /* dflags set in da850_evm_config_emac() */
1094*4882a593Smuzhiyun },
1095*4882a593Smuzhiyun { }
1096*4882a593Smuzhiyun };
1097*4882a593Smuzhiyun
da850_evm_config_emac(void)1098*4882a593Smuzhiyun static int __init da850_evm_config_emac(void)
1099*4882a593Smuzhiyun {
1100*4882a593Smuzhiyun void __iomem *cfg_chip3_base;
1101*4882a593Smuzhiyun int ret;
1102*4882a593Smuzhiyun u32 val;
1103*4882a593Smuzhiyun struct davinci_soc_info *soc_info = &davinci_soc_info;
1104*4882a593Smuzhiyun u8 rmii_en;
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun if (!machine_is_davinci_da850_evm())
1107*4882a593Smuzhiyun return 0;
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun rmii_en = soc_info->emac_pdata->rmii_en;
1110*4882a593Smuzhiyun
1111*4882a593Smuzhiyun cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
1112*4882a593Smuzhiyun
1113*4882a593Smuzhiyun val = __raw_readl(cfg_chip3_base);
1114*4882a593Smuzhiyun
1115*4882a593Smuzhiyun if (rmii_en) {
1116*4882a593Smuzhiyun val |= BIT(8);
1117*4882a593Smuzhiyun ret = davinci_cfg_reg_list(da850_evm_rmii_pins);
1118*4882a593Smuzhiyun pr_info("EMAC: RMII PHY configured, MII PHY will not be"
1119*4882a593Smuzhiyun " functional\n");
1120*4882a593Smuzhiyun } else {
1121*4882a593Smuzhiyun val &= ~BIT(8);
1122*4882a593Smuzhiyun ret = davinci_cfg_reg_list(da850_evm_mii_pins);
1123*4882a593Smuzhiyun pr_info("EMAC: MII PHY configured, RMII PHY will not be"
1124*4882a593Smuzhiyun " functional\n");
1125*4882a593Smuzhiyun }
1126*4882a593Smuzhiyun
1127*4882a593Smuzhiyun if (ret)
1128*4882a593Smuzhiyun pr_warn("%s: CPGMAC/RMII mux setup failed: %d\n",
1129*4882a593Smuzhiyun __func__, ret);
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun /* configure the CFGCHIP3 register for RMII or MII */
1132*4882a593Smuzhiyun __raw_writel(val, cfg_chip3_base);
1133*4882a593Smuzhiyun
1134*4882a593Smuzhiyun ret = davinci_cfg_reg(DA850_GPIO2_6);
1135*4882a593Smuzhiyun if (ret)
1136*4882a593Smuzhiyun pr_warn("%s:GPIO(2,6) mux setup failed\n", __func__);
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun da850_evm_emac_gpio_hogs[0].dflags = rmii_en ? GPIOD_OUT_HIGH
1139*4882a593Smuzhiyun : GPIOD_OUT_LOW;
1140*4882a593Smuzhiyun gpiod_add_hogs(da850_evm_emac_gpio_hogs);
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID;
1143*4882a593Smuzhiyun
1144*4882a593Smuzhiyun ret = da8xx_register_emac();
1145*4882a593Smuzhiyun if (ret)
1146*4882a593Smuzhiyun pr_warn("%s: EMAC registration failed: %d\n", __func__, ret);
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun return 0;
1149*4882a593Smuzhiyun }
1150*4882a593Smuzhiyun device_initcall(da850_evm_config_emac);
1151*4882a593Smuzhiyun
1152*4882a593Smuzhiyun /*
1153*4882a593Smuzhiyun * The following EDMA channels/slots are not being used by drivers (for
1154*4882a593Smuzhiyun * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence
1155*4882a593Smuzhiyun * they are being reserved for codecs on the DSP side.
1156*4882a593Smuzhiyun */
1157*4882a593Smuzhiyun static const s16 da850_dma0_rsv_chans[][2] = {
1158*4882a593Smuzhiyun /* (offset, number) */
1159*4882a593Smuzhiyun { 8, 6},
1160*4882a593Smuzhiyun {24, 4},
1161*4882a593Smuzhiyun {30, 2},
1162*4882a593Smuzhiyun {-1, -1}
1163*4882a593Smuzhiyun };
1164*4882a593Smuzhiyun
1165*4882a593Smuzhiyun static const s16 da850_dma0_rsv_slots[][2] = {
1166*4882a593Smuzhiyun /* (offset, number) */
1167*4882a593Smuzhiyun { 8, 6},
1168*4882a593Smuzhiyun {24, 4},
1169*4882a593Smuzhiyun {30, 50},
1170*4882a593Smuzhiyun {-1, -1}
1171*4882a593Smuzhiyun };
1172*4882a593Smuzhiyun
1173*4882a593Smuzhiyun static const s16 da850_dma1_rsv_chans[][2] = {
1174*4882a593Smuzhiyun /* (offset, number) */
1175*4882a593Smuzhiyun { 0, 28},
1176*4882a593Smuzhiyun {30, 2},
1177*4882a593Smuzhiyun {-1, -1}
1178*4882a593Smuzhiyun };
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun static const s16 da850_dma1_rsv_slots[][2] = {
1181*4882a593Smuzhiyun /* (offset, number) */
1182*4882a593Smuzhiyun { 0, 28},
1183*4882a593Smuzhiyun {30, 90},
1184*4882a593Smuzhiyun {-1, -1}
1185*4882a593Smuzhiyun };
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun static struct edma_rsv_info da850_edma_cc0_rsv = {
1188*4882a593Smuzhiyun .rsv_chans = da850_dma0_rsv_chans,
1189*4882a593Smuzhiyun .rsv_slots = da850_dma0_rsv_slots,
1190*4882a593Smuzhiyun };
1191*4882a593Smuzhiyun
1192*4882a593Smuzhiyun static struct edma_rsv_info da850_edma_cc1_rsv = {
1193*4882a593Smuzhiyun .rsv_chans = da850_dma1_rsv_chans,
1194*4882a593Smuzhiyun .rsv_slots = da850_dma1_rsv_slots,
1195*4882a593Smuzhiyun };
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun static struct edma_rsv_info *da850_edma_rsv[2] = {
1198*4882a593Smuzhiyun &da850_edma_cc0_rsv,
1199*4882a593Smuzhiyun &da850_edma_cc1_rsv,
1200*4882a593Smuzhiyun };
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun #ifdef CONFIG_CPU_FREQ
da850_evm_init_cpufreq(void)1203*4882a593Smuzhiyun static __init int da850_evm_init_cpufreq(void)
1204*4882a593Smuzhiyun {
1205*4882a593Smuzhiyun switch (system_rev & 0xF) {
1206*4882a593Smuzhiyun case 3:
1207*4882a593Smuzhiyun da850_max_speed = 456000;
1208*4882a593Smuzhiyun break;
1209*4882a593Smuzhiyun case 2:
1210*4882a593Smuzhiyun da850_max_speed = 408000;
1211*4882a593Smuzhiyun break;
1212*4882a593Smuzhiyun case 1:
1213*4882a593Smuzhiyun da850_max_speed = 372000;
1214*4882a593Smuzhiyun break;
1215*4882a593Smuzhiyun }
1216*4882a593Smuzhiyun
1217*4882a593Smuzhiyun return da850_register_cpufreq("pll0_sysclk3");
1218*4882a593Smuzhiyun }
1219*4882a593Smuzhiyun #else
da850_evm_init_cpufreq(void)1220*4882a593Smuzhiyun static __init int da850_evm_init_cpufreq(void) { return 0; }
1221*4882a593Smuzhiyun #endif
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun #if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
1224*4882a593Smuzhiyun
1225*4882a593Smuzhiyun #define TVP5147_CH0 "tvp514x-0"
1226*4882a593Smuzhiyun #define TVP5147_CH1 "tvp514x-1"
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun /* VPIF capture configuration */
1229*4882a593Smuzhiyun static struct tvp514x_platform_data tvp5146_pdata = {
1230*4882a593Smuzhiyun .clk_polarity = 0,
1231*4882a593Smuzhiyun .hs_polarity = 1,
1232*4882a593Smuzhiyun .vs_polarity = 1,
1233*4882a593Smuzhiyun };
1234*4882a593Smuzhiyun
1235*4882a593Smuzhiyun #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun static struct vpif_input da850_ch0_inputs[] = {
1238*4882a593Smuzhiyun {
1239*4882a593Smuzhiyun .input = {
1240*4882a593Smuzhiyun .index = 0,
1241*4882a593Smuzhiyun .name = "Composite",
1242*4882a593Smuzhiyun .type = V4L2_INPUT_TYPE_CAMERA,
1243*4882a593Smuzhiyun .capabilities = V4L2_IN_CAP_STD,
1244*4882a593Smuzhiyun .std = TVP514X_STD_ALL,
1245*4882a593Smuzhiyun },
1246*4882a593Smuzhiyun .input_route = INPUT_CVBS_VI2B,
1247*4882a593Smuzhiyun .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
1248*4882a593Smuzhiyun .subdev_name = TVP5147_CH0,
1249*4882a593Smuzhiyun },
1250*4882a593Smuzhiyun };
1251*4882a593Smuzhiyun
1252*4882a593Smuzhiyun static struct vpif_input da850_ch1_inputs[] = {
1253*4882a593Smuzhiyun {
1254*4882a593Smuzhiyun .input = {
1255*4882a593Smuzhiyun .index = 0,
1256*4882a593Smuzhiyun .name = "S-Video",
1257*4882a593Smuzhiyun .type = V4L2_INPUT_TYPE_CAMERA,
1258*4882a593Smuzhiyun .capabilities = V4L2_IN_CAP_STD,
1259*4882a593Smuzhiyun .std = TVP514X_STD_ALL,
1260*4882a593Smuzhiyun },
1261*4882a593Smuzhiyun .input_route = INPUT_SVIDEO_VI2C_VI1C,
1262*4882a593Smuzhiyun .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
1263*4882a593Smuzhiyun .subdev_name = TVP5147_CH1,
1264*4882a593Smuzhiyun },
1265*4882a593Smuzhiyun };
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = {
1268*4882a593Smuzhiyun {
1269*4882a593Smuzhiyun .name = TVP5147_CH0,
1270*4882a593Smuzhiyun .board_info = {
1271*4882a593Smuzhiyun I2C_BOARD_INFO("tvp5146", 0x5d),
1272*4882a593Smuzhiyun .platform_data = &tvp5146_pdata,
1273*4882a593Smuzhiyun },
1274*4882a593Smuzhiyun },
1275*4882a593Smuzhiyun {
1276*4882a593Smuzhiyun .name = TVP5147_CH1,
1277*4882a593Smuzhiyun .board_info = {
1278*4882a593Smuzhiyun I2C_BOARD_INFO("tvp5146", 0x5c),
1279*4882a593Smuzhiyun .platform_data = &tvp5146_pdata,
1280*4882a593Smuzhiyun },
1281*4882a593Smuzhiyun },
1282*4882a593Smuzhiyun };
1283*4882a593Smuzhiyun
1284*4882a593Smuzhiyun static struct vpif_capture_config da850_vpif_capture_config = {
1285*4882a593Smuzhiyun .subdev_info = da850_vpif_capture_sdev_info,
1286*4882a593Smuzhiyun .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info),
1287*4882a593Smuzhiyun .i2c_adapter_id = 1,
1288*4882a593Smuzhiyun .chan_config[0] = {
1289*4882a593Smuzhiyun .inputs = da850_ch0_inputs,
1290*4882a593Smuzhiyun .input_count = ARRAY_SIZE(da850_ch0_inputs),
1291*4882a593Smuzhiyun .vpif_if = {
1292*4882a593Smuzhiyun .if_type = VPIF_IF_BT656,
1293*4882a593Smuzhiyun .hd_pol = 1,
1294*4882a593Smuzhiyun .vd_pol = 1,
1295*4882a593Smuzhiyun .fid_pol = 0,
1296*4882a593Smuzhiyun },
1297*4882a593Smuzhiyun },
1298*4882a593Smuzhiyun .chan_config[1] = {
1299*4882a593Smuzhiyun .inputs = da850_ch1_inputs,
1300*4882a593Smuzhiyun .input_count = ARRAY_SIZE(da850_ch1_inputs),
1301*4882a593Smuzhiyun .vpif_if = {
1302*4882a593Smuzhiyun .if_type = VPIF_IF_BT656,
1303*4882a593Smuzhiyun .hd_pol = 1,
1304*4882a593Smuzhiyun .vd_pol = 1,
1305*4882a593Smuzhiyun .fid_pol = 0,
1306*4882a593Smuzhiyun },
1307*4882a593Smuzhiyun },
1308*4882a593Smuzhiyun .card_name = "DA850/OMAP-L138 Video Capture",
1309*4882a593Smuzhiyun };
1310*4882a593Smuzhiyun
1311*4882a593Smuzhiyun /* VPIF display configuration */
1312*4882a593Smuzhiyun
1313*4882a593Smuzhiyun static struct adv7343_platform_data adv7343_pdata = {
1314*4882a593Smuzhiyun .mode_config = {
1315*4882a593Smuzhiyun .dac = { 1, 1, 1 },
1316*4882a593Smuzhiyun },
1317*4882a593Smuzhiyun .sd_config = {
1318*4882a593Smuzhiyun .sd_dac_out = { 1 },
1319*4882a593Smuzhiyun },
1320*4882a593Smuzhiyun };
1321*4882a593Smuzhiyun
1322*4882a593Smuzhiyun static struct vpif_subdev_info da850_vpif_subdev[] = {
1323*4882a593Smuzhiyun {
1324*4882a593Smuzhiyun .name = "adv7343",
1325*4882a593Smuzhiyun .board_info = {
1326*4882a593Smuzhiyun I2C_BOARD_INFO("adv7343", 0x2a),
1327*4882a593Smuzhiyun .platform_data = &adv7343_pdata,
1328*4882a593Smuzhiyun },
1329*4882a593Smuzhiyun },
1330*4882a593Smuzhiyun };
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun static const struct vpif_output da850_ch0_outputs[] = {
1333*4882a593Smuzhiyun {
1334*4882a593Smuzhiyun .output = {
1335*4882a593Smuzhiyun .index = 0,
1336*4882a593Smuzhiyun .name = "Composite",
1337*4882a593Smuzhiyun .type = V4L2_OUTPUT_TYPE_ANALOG,
1338*4882a593Smuzhiyun .capabilities = V4L2_OUT_CAP_STD,
1339*4882a593Smuzhiyun .std = V4L2_STD_ALL,
1340*4882a593Smuzhiyun },
1341*4882a593Smuzhiyun .subdev_name = "adv7343",
1342*4882a593Smuzhiyun .output_route = ADV7343_COMPOSITE_ID,
1343*4882a593Smuzhiyun },
1344*4882a593Smuzhiyun {
1345*4882a593Smuzhiyun .output = {
1346*4882a593Smuzhiyun .index = 1,
1347*4882a593Smuzhiyun .name = "S-Video",
1348*4882a593Smuzhiyun .type = V4L2_OUTPUT_TYPE_ANALOG,
1349*4882a593Smuzhiyun .capabilities = V4L2_OUT_CAP_STD,
1350*4882a593Smuzhiyun .std = V4L2_STD_ALL,
1351*4882a593Smuzhiyun },
1352*4882a593Smuzhiyun .subdev_name = "adv7343",
1353*4882a593Smuzhiyun .output_route = ADV7343_SVIDEO_ID,
1354*4882a593Smuzhiyun },
1355*4882a593Smuzhiyun };
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun static struct vpif_display_config da850_vpif_display_config = {
1358*4882a593Smuzhiyun .subdevinfo = da850_vpif_subdev,
1359*4882a593Smuzhiyun .subdev_count = ARRAY_SIZE(da850_vpif_subdev),
1360*4882a593Smuzhiyun .chan_config[0] = {
1361*4882a593Smuzhiyun .outputs = da850_ch0_outputs,
1362*4882a593Smuzhiyun .output_count = ARRAY_SIZE(da850_ch0_outputs),
1363*4882a593Smuzhiyun },
1364*4882a593Smuzhiyun .card_name = "DA850/OMAP-L138 Video Display",
1365*4882a593Smuzhiyun .i2c_adapter_id = 1,
1366*4882a593Smuzhiyun };
1367*4882a593Smuzhiyun
da850_vpif_init(void)1368*4882a593Smuzhiyun static __init void da850_vpif_init(void)
1369*4882a593Smuzhiyun {
1370*4882a593Smuzhiyun int ret;
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun ret = da850_register_vpif();
1373*4882a593Smuzhiyun if (ret)
1374*4882a593Smuzhiyun pr_warn("da850_evm_init: VPIF setup failed: %d\n", ret);
1375*4882a593Smuzhiyun
1376*4882a593Smuzhiyun ret = davinci_cfg_reg_list(da850_vpif_capture_pins);
1377*4882a593Smuzhiyun if (ret)
1378*4882a593Smuzhiyun pr_warn("da850_evm_init: VPIF capture mux setup failed: %d\n",
1379*4882a593Smuzhiyun ret);
1380*4882a593Smuzhiyun
1381*4882a593Smuzhiyun ret = da850_register_vpif_capture(&da850_vpif_capture_config);
1382*4882a593Smuzhiyun if (ret)
1383*4882a593Smuzhiyun pr_warn("da850_evm_init: VPIF capture setup failed: %d\n", ret);
1384*4882a593Smuzhiyun
1385*4882a593Smuzhiyun ret = davinci_cfg_reg_list(da850_vpif_display_pins);
1386*4882a593Smuzhiyun if (ret)
1387*4882a593Smuzhiyun pr_warn("da850_evm_init: VPIF display mux setup failed: %d\n",
1388*4882a593Smuzhiyun ret);
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun ret = da850_register_vpif_display(&da850_vpif_display_config);
1391*4882a593Smuzhiyun if (ret)
1392*4882a593Smuzhiyun pr_warn("da850_evm_init: VPIF display setup failed: %d\n", ret);
1393*4882a593Smuzhiyun }
1394*4882a593Smuzhiyun
1395*4882a593Smuzhiyun #else
da850_vpif_init(void)1396*4882a593Smuzhiyun static __init void da850_vpif_init(void) {}
1397*4882a593Smuzhiyun #endif
1398*4882a593Smuzhiyun
1399*4882a593Smuzhiyun #define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000)
1400*4882a593Smuzhiyun
da850_evm_init(void)1401*4882a593Smuzhiyun static __init void da850_evm_init(void)
1402*4882a593Smuzhiyun {
1403*4882a593Smuzhiyun int ret;
1404*4882a593Smuzhiyun
1405*4882a593Smuzhiyun da850_register_clocks();
1406*4882a593Smuzhiyun
1407*4882a593Smuzhiyun ret = da850_register_gpio();
1408*4882a593Smuzhiyun if (ret)
1409*4882a593Smuzhiyun pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
1410*4882a593Smuzhiyun
1411*4882a593Smuzhiyun regulator_register_fixed(0, fixed_supplies, ARRAY_SIZE(fixed_supplies));
1412*4882a593Smuzhiyun
1413*4882a593Smuzhiyun ret = pmic_tps65070_init();
1414*4882a593Smuzhiyun if (ret)
1415*4882a593Smuzhiyun pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret);
1416*4882a593Smuzhiyun
1417*4882a593Smuzhiyun ret = da850_register_edma(da850_edma_rsv);
1418*4882a593Smuzhiyun if (ret)
1419*4882a593Smuzhiyun pr_warn("%s: EDMA registration failed: %d\n", __func__, ret);
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun ret = davinci_cfg_reg_list(da850_i2c0_pins);
1422*4882a593Smuzhiyun if (ret)
1423*4882a593Smuzhiyun pr_warn("%s: I2C0 mux setup failed: %d\n", __func__, ret);
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata);
1426*4882a593Smuzhiyun if (ret)
1427*4882a593Smuzhiyun pr_warn("%s: I2C0 registration failed: %d\n", __func__, ret);
1428*4882a593Smuzhiyun
1429*4882a593Smuzhiyun
1430*4882a593Smuzhiyun ret = da8xx_register_watchdog();
1431*4882a593Smuzhiyun if (ret)
1432*4882a593Smuzhiyun pr_warn("%s: watchdog registration failed: %d\n",
1433*4882a593Smuzhiyun __func__, ret);
1434*4882a593Smuzhiyun
1435*4882a593Smuzhiyun if (HAS_MMC) {
1436*4882a593Smuzhiyun ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins);
1437*4882a593Smuzhiyun if (ret)
1438*4882a593Smuzhiyun pr_warn("%s: MMCSD0 mux setup failed: %d\n",
1439*4882a593Smuzhiyun __func__, ret);
1440*4882a593Smuzhiyun
1441*4882a593Smuzhiyun gpiod_add_lookup_table(&mmc_gpios_table);
1442*4882a593Smuzhiyun
1443*4882a593Smuzhiyun ret = da8xx_register_mmcsd0(&da850_mmc_config);
1444*4882a593Smuzhiyun if (ret)
1445*4882a593Smuzhiyun pr_warn("%s: MMCSD0 registration failed: %d\n",
1446*4882a593Smuzhiyun __func__, ret);
1447*4882a593Smuzhiyun }
1448*4882a593Smuzhiyun
1449*4882a593Smuzhiyun davinci_serial_init(da8xx_serial_device);
1450*4882a593Smuzhiyun
1451*4882a593Smuzhiyun nvmem_add_cell_table(&da850evm_nvmem_cell_table);
1452*4882a593Smuzhiyun nvmem_add_cell_lookups(&da850evm_nvmem_cell_lookup, 1);
1453*4882a593Smuzhiyun
1454*4882a593Smuzhiyun i2c_register_board_info(1, da850_evm_i2c_devices,
1455*4882a593Smuzhiyun ARRAY_SIZE(da850_evm_i2c_devices));
1456*4882a593Smuzhiyun
1457*4882a593Smuzhiyun /*
1458*4882a593Smuzhiyun * shut down uart 0 and 1; they are not used on the board and
1459*4882a593Smuzhiyun * accessing them causes endless "too much work in irq53" messages
1460*4882a593Smuzhiyun * with arago fs
1461*4882a593Smuzhiyun */
1462*4882a593Smuzhiyun __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
1463*4882a593Smuzhiyun __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
1464*4882a593Smuzhiyun
1465*4882a593Smuzhiyun ret = davinci_cfg_reg_list(da850_evm_mcasp_pins);
1466*4882a593Smuzhiyun if (ret)
1467*4882a593Smuzhiyun pr_warn("%s: McASP mux setup failed: %d\n", __func__, ret);
1468*4882a593Smuzhiyun
1469*4882a593Smuzhiyun da850_evm_snd_data.sram_pool = sram_get_gen_pool();
1470*4882a593Smuzhiyun da8xx_register_mcasp(0, &da850_evm_snd_data);
1471*4882a593Smuzhiyun
1472*4882a593Smuzhiyun ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
1473*4882a593Smuzhiyun if (ret)
1474*4882a593Smuzhiyun pr_warn("%s: LCDC mux setup failed: %d\n", __func__, ret);
1475*4882a593Smuzhiyun
1476*4882a593Smuzhiyun ret = da8xx_register_uio_pruss();
1477*4882a593Smuzhiyun if (ret)
1478*4882a593Smuzhiyun pr_warn("da850_evm_init: pruss initialization failed: %d\n",
1479*4882a593Smuzhiyun ret);
1480*4882a593Smuzhiyun
1481*4882a593Smuzhiyun /* Handle board specific muxing for LCD here */
1482*4882a593Smuzhiyun ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
1483*4882a593Smuzhiyun if (ret)
1484*4882a593Smuzhiyun pr_warn("%s: EVM specific LCD mux setup failed: %d\n",
1485*4882a593Smuzhiyun __func__, ret);
1486*4882a593Smuzhiyun
1487*4882a593Smuzhiyun ret = da850_lcd_hw_init();
1488*4882a593Smuzhiyun if (ret)
1489*4882a593Smuzhiyun pr_warn("%s: LCD initialization failed: %d\n", __func__, ret);
1490*4882a593Smuzhiyun
1491*4882a593Smuzhiyun ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata);
1492*4882a593Smuzhiyun if (ret)
1493*4882a593Smuzhiyun pr_warn("%s: LCDC registration failed: %d\n", __func__, ret);
1494*4882a593Smuzhiyun
1495*4882a593Smuzhiyun ret = da8xx_register_rtc();
1496*4882a593Smuzhiyun if (ret)
1497*4882a593Smuzhiyun pr_warn("%s: RTC setup failed: %d\n", __func__, ret);
1498*4882a593Smuzhiyun
1499*4882a593Smuzhiyun ret = da850_evm_init_cpufreq();
1500*4882a593Smuzhiyun if (ret)
1501*4882a593Smuzhiyun pr_warn("%s: cpufreq registration failed: %d\n", __func__, ret);
1502*4882a593Smuzhiyun
1503*4882a593Smuzhiyun ret = da8xx_register_cpuidle();
1504*4882a593Smuzhiyun if (ret)
1505*4882a593Smuzhiyun pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret);
1506*4882a593Smuzhiyun
1507*4882a593Smuzhiyun davinci_pm_init();
1508*4882a593Smuzhiyun da850_vpif_init();
1509*4882a593Smuzhiyun
1510*4882a593Smuzhiyun ret = spi_register_board_info(da850evm_spi_info,
1511*4882a593Smuzhiyun ARRAY_SIZE(da850evm_spi_info));
1512*4882a593Smuzhiyun if (ret)
1513*4882a593Smuzhiyun pr_warn("%s: spi info registration failed: %d\n", __func__,
1514*4882a593Smuzhiyun ret);
1515*4882a593Smuzhiyun
1516*4882a593Smuzhiyun ret = da8xx_register_spi_bus(1, ARRAY_SIZE(da850evm_spi_info));
1517*4882a593Smuzhiyun if (ret)
1518*4882a593Smuzhiyun pr_warn("%s: SPI 1 registration failed: %d\n", __func__, ret);
1519*4882a593Smuzhiyun
1520*4882a593Smuzhiyun ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE);
1521*4882a593Smuzhiyun if (ret)
1522*4882a593Smuzhiyun pr_warn("%s: SATA registration failed: %d\n", __func__, ret);
1523*4882a593Smuzhiyun
1524*4882a593Smuzhiyun ret = da8xx_register_rproc();
1525*4882a593Smuzhiyun if (ret)
1526*4882a593Smuzhiyun pr_warn("%s: dsp/rproc registration failed: %d\n",
1527*4882a593Smuzhiyun __func__, ret);
1528*4882a593Smuzhiyun
1529*4882a593Smuzhiyun regulator_has_full_constraints();
1530*4882a593Smuzhiyun }
1531*4882a593Smuzhiyun
1532*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250_CONSOLE
da850_evm_console_init(void)1533*4882a593Smuzhiyun static int __init da850_evm_console_init(void)
1534*4882a593Smuzhiyun {
1535*4882a593Smuzhiyun if (!machine_is_davinci_da850_evm())
1536*4882a593Smuzhiyun return 0;
1537*4882a593Smuzhiyun
1538*4882a593Smuzhiyun return add_preferred_console("ttyS", 2, "115200");
1539*4882a593Smuzhiyun }
1540*4882a593Smuzhiyun console_initcall(da850_evm_console_init);
1541*4882a593Smuzhiyun #endif
1542*4882a593Smuzhiyun
da850_evm_map_io(void)1543*4882a593Smuzhiyun static void __init da850_evm_map_io(void)
1544*4882a593Smuzhiyun {
1545*4882a593Smuzhiyun da850_init();
1546*4882a593Smuzhiyun }
1547*4882a593Smuzhiyun
1548*4882a593Smuzhiyun MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
1549*4882a593Smuzhiyun .atag_offset = 0x100,
1550*4882a593Smuzhiyun .map_io = da850_evm_map_io,
1551*4882a593Smuzhiyun .init_irq = da850_init_irq,
1552*4882a593Smuzhiyun .init_time = da850_init_time,
1553*4882a593Smuzhiyun .init_machine = da850_evm_init,
1554*4882a593Smuzhiyun .init_late = davinci_init_late,
1555*4882a593Smuzhiyun .dma_zone_size = SZ_128M,
1556*4882a593Smuzhiyun .reserve = da8xx_rproc_reserve_cma,
1557*4882a593Smuzhiyun MACHINE_END
1558