1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * TI DaVinci Audio definitions 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __ASM_ARCH_DAVINCI_ASP_H 6*4882a593Smuzhiyun #define __ASM_ARCH_DAVINCI_ASP_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* Bases of dm644x and dm355 register banks */ 9*4882a593Smuzhiyun #define DAVINCI_ASP0_BASE 0x01E02000 10*4882a593Smuzhiyun #define DAVINCI_ASP1_BASE 0x01E04000 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Bases of dm365 register banks */ 13*4882a593Smuzhiyun #define DAVINCI_DM365_ASP0_BASE 0x01D02000 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Bases of dm646x register banks */ 16*4882a593Smuzhiyun #define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 17*4882a593Smuzhiyun #define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Bases of da850/da830 McASP0 register banks */ 20*4882a593Smuzhiyun #define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Bases of da830 McASP1 register banks */ 23*4882a593Smuzhiyun #define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Bases of da830 McASP2 register banks */ 26*4882a593Smuzhiyun #define DAVINCI_DA830_MCASP2_REG_BASE 0x01D08000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* EDMA channels of dm644x and dm355 */ 29*4882a593Smuzhiyun #define DAVINCI_DMA_ASP0_TX 2 30*4882a593Smuzhiyun #define DAVINCI_DMA_ASP0_RX 3 31*4882a593Smuzhiyun #define DAVINCI_DMA_ASP1_TX 8 32*4882a593Smuzhiyun #define DAVINCI_DMA_ASP1_RX 9 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* EDMA channels of dm646x */ 35*4882a593Smuzhiyun #define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 36*4882a593Smuzhiyun #define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 37*4882a593Smuzhiyun #define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* EDMA channels of da850/da830 McASP0 */ 40*4882a593Smuzhiyun #define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 41*4882a593Smuzhiyun #define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* EDMA channels of da830 McASP1 */ 44*4882a593Smuzhiyun #define DAVINCI_DA830_DMA_MCASP1_AREVT 2 45*4882a593Smuzhiyun #define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* EDMA channels of da830 McASP2 */ 48*4882a593Smuzhiyun #define DAVINCI_DA830_DMA_MCASP2_AREVT 4 49*4882a593Smuzhiyun #define DAVINCI_DA830_DMA_MCASP2_AXEVT 5 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Interrupts */ 52*4882a593Smuzhiyun #define DAVINCI_ASP0_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT) 53*4882a593Smuzhiyun #define DAVINCI_ASP0_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT) 54*4882a593Smuzhiyun #define DAVINCI_ASP1_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT) 55*4882a593Smuzhiyun #define DAVINCI_ASP1_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif /* __ASM_ARCH_DAVINCI_ASP_H */ 58