1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * CNS3xxx common devices
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2008 Cavium Networks
6*4882a593Smuzhiyun * Scott Shu
7*4882a593Smuzhiyun * Copyright 2010 MontaVista Software, LLC.
8*4882a593Smuzhiyun * Anton Vorontsov <avorontsov@mvista.com>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/compiler.h>
14*4882a593Smuzhiyun #include <linux/dma-mapping.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include "cns3xxx.h"
17*4882a593Smuzhiyun #include "pm.h"
18*4882a593Smuzhiyun #include "core.h"
19*4882a593Smuzhiyun #include "devices.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /*
22*4882a593Smuzhiyun * AHCI
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun static struct resource cns3xxx_ahci_resource[] = {
25*4882a593Smuzhiyun [0] = {
26*4882a593Smuzhiyun .start = CNS3XXX_SATA2_BASE,
27*4882a593Smuzhiyun .end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
28*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
29*4882a593Smuzhiyun },
30*4882a593Smuzhiyun [1] = {
31*4882a593Smuzhiyun .start = IRQ_CNS3XXX_SATA,
32*4882a593Smuzhiyun .end = IRQ_CNS3XXX_SATA,
33*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
34*4882a593Smuzhiyun },
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static struct platform_device cns3xxx_ahci_pdev = {
40*4882a593Smuzhiyun .name = "ahci",
41*4882a593Smuzhiyun .id = 0,
42*4882a593Smuzhiyun .resource = cns3xxx_ahci_resource,
43*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(cns3xxx_ahci_resource),
44*4882a593Smuzhiyun .dev = {
45*4882a593Smuzhiyun .dma_mask = &cns3xxx_ahci_dmamask,
46*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
47*4882a593Smuzhiyun },
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
cns3xxx_ahci_init(void)50*4882a593Smuzhiyun void __init cns3xxx_ahci_init(void)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun u32 tmp;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun tmp = __raw_readl(MISC_SATA_POWER_MODE);
55*4882a593Smuzhiyun tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
56*4882a593Smuzhiyun tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
57*4882a593Smuzhiyun __raw_writel(tmp, MISC_SATA_POWER_MODE);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Enable SATA PHY */
60*4882a593Smuzhiyun cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
61*4882a593Smuzhiyun cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Enable SATA Clock */
64*4882a593Smuzhiyun cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* De-Asscer SATA Reset */
67*4882a593Smuzhiyun cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun platform_device_register(&cns3xxx_ahci_pdev);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /*
73*4882a593Smuzhiyun * SDHCI
74*4882a593Smuzhiyun */
75*4882a593Smuzhiyun static struct resource cns3xxx_sdhci_resources[] = {
76*4882a593Smuzhiyun [0] = {
77*4882a593Smuzhiyun .start = CNS3XXX_SDIO_BASE,
78*4882a593Smuzhiyun .end = CNS3XXX_SDIO_BASE + SZ_4K - 1,
79*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
80*4882a593Smuzhiyun },
81*4882a593Smuzhiyun [1] = {
82*4882a593Smuzhiyun .start = IRQ_CNS3XXX_SDIO,
83*4882a593Smuzhiyun .end = IRQ_CNS3XXX_SDIO,
84*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
85*4882a593Smuzhiyun },
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static struct platform_device cns3xxx_sdhci_pdev = {
89*4882a593Smuzhiyun .name = "sdhci-cns3xxx",
90*4882a593Smuzhiyun .id = 0,
91*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(cns3xxx_sdhci_resources),
92*4882a593Smuzhiyun .resource = cns3xxx_sdhci_resources,
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
cns3xxx_sdhci_init(void)95*4882a593Smuzhiyun void __init cns3xxx_sdhci_init(void)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
98*4882a593Smuzhiyun u32 gpioa_pins = __raw_readl(gpioa);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* MMC/SD pins share with GPIOA */
101*4882a593Smuzhiyun gpioa_pins |= 0x1fff0004;
102*4882a593Smuzhiyun __raw_writel(gpioa_pins, gpioa);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
105*4882a593Smuzhiyun cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun platform_device_register(&cns3xxx_sdhci_pdev);
108*4882a593Smuzhiyun }
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