1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/arch/arm/mach-axxia/platsmp.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2012 LSI Corporation
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/smp.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun #include <asm/cacheflush.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /* Syscon register offsets for releasing cores from reset */
16*4882a593Smuzhiyun #define SC_CRIT_WRITE_KEY 0x1000
17*4882a593Smuzhiyun #define SC_RST_CPU_HOLD 0x1010
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * Write the kernel entry point for secondary CPUs to the specified address
21*4882a593Smuzhiyun */
write_release_addr(u32 release_phys)22*4882a593Smuzhiyun static void write_release_addr(u32 release_phys)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun u32 *virt = (u32 *) phys_to_virt(release_phys);
25*4882a593Smuzhiyun writel_relaxed(__pa_symbol(secondary_startup), virt);
26*4882a593Smuzhiyun /* Make sure this store is visible to other CPUs */
27*4882a593Smuzhiyun smp_wmb();
28*4882a593Smuzhiyun __cpuc_flush_dcache_area(virt, sizeof(u32));
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
axxia_boot_secondary(unsigned int cpu,struct task_struct * idle)31*4882a593Smuzhiyun static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun struct device_node *syscon_np;
34*4882a593Smuzhiyun void __iomem *syscon;
35*4882a593Smuzhiyun u32 tmp;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun syscon_np = of_find_compatible_node(NULL, NULL, "lsi,axxia-syscon");
38*4882a593Smuzhiyun if (!syscon_np)
39*4882a593Smuzhiyun return -ENOENT;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun syscon = of_iomap(syscon_np, 0);
42*4882a593Smuzhiyun of_node_put(syscon_np);
43*4882a593Smuzhiyun if (!syscon)
44*4882a593Smuzhiyun return -ENOMEM;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun tmp = readl(syscon + SC_RST_CPU_HOLD);
47*4882a593Smuzhiyun writel(0xab, syscon + SC_CRIT_WRITE_KEY);
48*4882a593Smuzhiyun tmp &= ~(1 << cpu);
49*4882a593Smuzhiyun writel(tmp, syscon + SC_RST_CPU_HOLD);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return 0;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
axxia_smp_prepare_cpus(unsigned int max_cpus)54*4882a593Smuzhiyun static void __init axxia_smp_prepare_cpus(unsigned int max_cpus)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun int cpu_count = 0;
57*4882a593Smuzhiyun int cpu;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun * Initialise the present map, which describes the set of CPUs actually
61*4882a593Smuzhiyun * populated at the present time.
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun for_each_possible_cpu(cpu) {
64*4882a593Smuzhiyun struct device_node *np;
65*4882a593Smuzhiyun u32 release_phys;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun np = of_get_cpu_node(cpu, NULL);
68*4882a593Smuzhiyun if (!np)
69*4882a593Smuzhiyun continue;
70*4882a593Smuzhiyun if (of_property_read_u32(np, "cpu-release-addr", &release_phys))
71*4882a593Smuzhiyun continue;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (cpu_count < max_cpus) {
74*4882a593Smuzhiyun set_cpu_present(cpu, true);
75*4882a593Smuzhiyun cpu_count++;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (release_phys != 0)
79*4882a593Smuzhiyun write_release_addr(release_phys);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static const struct smp_operations axxia_smp_ops __initconst = {
84*4882a593Smuzhiyun .smp_prepare_cpus = axxia_smp_prepare_cpus,
85*4882a593Smuzhiyun .smp_boot_secondary = axxia_boot_secondary,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun CPU_METHOD_OF_DECLARE(axxia_smp, "lsi,syscon-release", &axxia_smp_ops);
88