1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ARTPEC-6 device support.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/amba/bus.h>
7*4882a593Smuzhiyun #include <linux/clocksource.h>
8*4882a593Smuzhiyun #include <linux/dma-mapping.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/irqchip.h>
11*4882a593Smuzhiyun #include <linux/irqchip/arm-gic.h>
12*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_address.h>
15*4882a593Smuzhiyun #include <linux/clk-provider.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun #include <linux/smp.h>
18*4882a593Smuzhiyun #include <asm/smp_scu.h>
19*4882a593Smuzhiyun #include <asm/mach/arch.h>
20*4882a593Smuzhiyun #include <asm/mach/map.h>
21*4882a593Smuzhiyun #include <asm/psci.h>
22*4882a593Smuzhiyun #include <linux/arm-smccc.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define ARTPEC6_DMACFG_REGNUM 0x10
26*4882a593Smuzhiyun #define ARTPEC6_DMACFG_UARTS_BURST 0xff
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define SECURE_OP_L2C_WRITEREG 0xb4000001
29*4882a593Smuzhiyun
artpec6_init_machine(void)30*4882a593Smuzhiyun static void __init artpec6_init_machine(void)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct regmap *regmap;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun regmap = syscon_regmap_lookup_by_compatible("axis,artpec6-syscon");
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if (!IS_ERR(regmap)) {
37*4882a593Smuzhiyun /* Use PL011 DMA Burst Request signal instead of DMA
38*4882a593Smuzhiyun * Single Request
39*4882a593Smuzhiyun */
40*4882a593Smuzhiyun regmap_write(regmap, ARTPEC6_DMACFG_REGNUM,
41*4882a593Smuzhiyun ARTPEC6_DMACFG_UARTS_BURST);
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
artpec6_l2c310_write_sec(unsigned long val,unsigned reg)45*4882a593Smuzhiyun static void artpec6_l2c310_write_sec(unsigned long val, unsigned reg)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct arm_smccc_res res;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun arm_smccc_smc(SECURE_OP_L2C_WRITEREG, reg, val, 0,
50*4882a593Smuzhiyun 0, 0, 0, 0, &res);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun WARN_ON(res.a0);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static const char * const artpec6_dt_match[] = {
56*4882a593Smuzhiyun "axis,artpec6",
57*4882a593Smuzhiyun NULL
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun DT_MACHINE_START(ARTPEC6, "Axis ARTPEC-6 Platform")
61*4882a593Smuzhiyun .l2c_aux_val = 0x0C000000,
62*4882a593Smuzhiyun .l2c_aux_mask = 0xF3FFFFFF,
63*4882a593Smuzhiyun .l2c_write_sec = artpec6_l2c310_write_sec,
64*4882a593Smuzhiyun .init_machine = artpec6_init_machine,
65*4882a593Smuzhiyun .dt_compat = artpec6_dt_match,
66*4882a593Smuzhiyun MACHINE_END
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