1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Annapurna labs cpu-resume register structure. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Annapurna Labs Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef ALPINE_CPU_RESUME_H_ 9*4882a593Smuzhiyun #define ALPINE_CPU_RESUME_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Per-cpu regs */ 12*4882a593Smuzhiyun struct al_cpu_resume_regs_per_cpu { 13*4882a593Smuzhiyun uint32_t flags; 14*4882a593Smuzhiyun uint32_t resume_addr; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* general regs */ 18*4882a593Smuzhiyun struct al_cpu_resume_regs { 19*4882a593Smuzhiyun /* Watermark for validating the CPU resume struct */ 20*4882a593Smuzhiyun uint32_t watermark; 21*4882a593Smuzhiyun uint32_t flags; 22*4882a593Smuzhiyun struct al_cpu_resume_regs_per_cpu per_cpu[]; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* The expected magic number for validating the resume addresses */ 26*4882a593Smuzhiyun #define AL_CPU_RESUME_MAGIC_NUM 0xf0e1d200 27*4882a593Smuzhiyun #define AL_CPU_RESUME_MAGIC_NUM_MASK 0xffffff00 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #endif /* ALPINE_CPU_RESUME_H_ */ 30