1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * linux/arch/arm/lib/io-readsw-armv3.S 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1995-2000 Russell King 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun#include <linux/linkage.h> 8*4882a593Smuzhiyun#include <asm/assembler.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun.Linsw_bad_alignment: 11*4882a593Smuzhiyun adr r0, .Linsw_bad_align_msg 12*4882a593Smuzhiyun mov r2, lr 13*4882a593Smuzhiyun b panic 14*4882a593Smuzhiyun.Linsw_bad_align_msg: 15*4882a593Smuzhiyun .asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n" 16*4882a593Smuzhiyun .align 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun.Linsw_align: tst r1, #1 19*4882a593Smuzhiyun bne .Linsw_bad_alignment 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun ldr r3, [r0] 22*4882a593Smuzhiyun strb r3, [r1], #1 23*4882a593Smuzhiyun mov r3, r3, lsr #8 24*4882a593Smuzhiyun strb r3, [r1], #1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun subs r2, r2, #1 27*4882a593Smuzhiyun reteq lr 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunENTRY(__raw_readsw) 30*4882a593Smuzhiyun teq r2, #0 @ do we have to check for the zero len? 31*4882a593Smuzhiyun reteq lr 32*4882a593Smuzhiyun tst r1, #3 33*4882a593Smuzhiyun bne .Linsw_align 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun.Linsw_aligned: mov ip, #0xff 36*4882a593Smuzhiyun orr ip, ip, ip, lsl #8 37*4882a593Smuzhiyun stmfd sp!, {r4, r5, r6, lr} 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun subs r2, r2, #8 40*4882a593Smuzhiyun bmi .Lno_insw_8 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun.Linsw_8_lp: ldr r3, [r0] 43*4882a593Smuzhiyun and r3, r3, ip 44*4882a593Smuzhiyun ldr r4, [r0] 45*4882a593Smuzhiyun orr r3, r3, r4, lsl #16 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun ldr r4, [r0] 48*4882a593Smuzhiyun and r4, r4, ip 49*4882a593Smuzhiyun ldr r5, [r0] 50*4882a593Smuzhiyun orr r4, r4, r5, lsl #16 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun ldr r5, [r0] 53*4882a593Smuzhiyun and r5, r5, ip 54*4882a593Smuzhiyun ldr r6, [r0] 55*4882a593Smuzhiyun orr r5, r5, r6, lsl #16 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun ldr r6, [r0] 58*4882a593Smuzhiyun and r6, r6, ip 59*4882a593Smuzhiyun ldr lr, [r0] 60*4882a593Smuzhiyun orr r6, r6, lr, lsl #16 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun stmia r1!, {r3 - r6} 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun subs r2, r2, #8 65*4882a593Smuzhiyun bpl .Linsw_8_lp 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun tst r2, #7 68*4882a593Smuzhiyun ldmfdeq sp!, {r4, r5, r6, pc} 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun.Lno_insw_8: tst r2, #4 71*4882a593Smuzhiyun beq .Lno_insw_4 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun ldr r3, [r0] 74*4882a593Smuzhiyun and r3, r3, ip 75*4882a593Smuzhiyun ldr r4, [r0] 76*4882a593Smuzhiyun orr r3, r3, r4, lsl #16 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun ldr r4, [r0] 79*4882a593Smuzhiyun and r4, r4, ip 80*4882a593Smuzhiyun ldr r5, [r0] 81*4882a593Smuzhiyun orr r4, r4, r5, lsl #16 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun stmia r1!, {r3, r4} 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun.Lno_insw_4: tst r2, #2 86*4882a593Smuzhiyun beq .Lno_insw_2 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun ldr r3, [r0] 89*4882a593Smuzhiyun and r3, r3, ip 90*4882a593Smuzhiyun ldr r4, [r0] 91*4882a593Smuzhiyun orr r3, r3, r4, lsl #16 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun str r3, [r1], #4 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun.Lno_insw_2: tst r2, #1 96*4882a593Smuzhiyun ldrne r3, [r0] 97*4882a593Smuzhiyun strbne r3, [r1], #1 98*4882a593Smuzhiyun movne r3, r3, lsr #8 99*4882a593Smuzhiyun strbne r3, [r1] 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun ldmfd sp!, {r4, r5, r6, pc} 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun 104