1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/arch/arm/kernel/opcodes.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * A32 condition code lookup feature moved from nwfpe/fpopcode.c
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <asm/opcodes.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define ARM_OPCODE_CONDITION_UNCOND 0xf
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun * condition code lookup table
15*4882a593Smuzhiyun * index into the table is test code: EQ, NE, ... LT, GT, AL, NV
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * bit position in short is condition code: NZCV
18*4882a593Smuzhiyun */
19*4882a593Smuzhiyun static const unsigned short cc_map[16] = {
20*4882a593Smuzhiyun 0xF0F0, /* EQ == Z set */
21*4882a593Smuzhiyun 0x0F0F, /* NE */
22*4882a593Smuzhiyun 0xCCCC, /* CS == C set */
23*4882a593Smuzhiyun 0x3333, /* CC */
24*4882a593Smuzhiyun 0xFF00, /* MI == N set */
25*4882a593Smuzhiyun 0x00FF, /* PL */
26*4882a593Smuzhiyun 0xAAAA, /* VS == V set */
27*4882a593Smuzhiyun 0x5555, /* VC */
28*4882a593Smuzhiyun 0x0C0C, /* HI == C set && Z clear */
29*4882a593Smuzhiyun 0xF3F3, /* LS == C clear || Z set */
30*4882a593Smuzhiyun 0xAA55, /* GE == (N==V) */
31*4882a593Smuzhiyun 0x55AA, /* LT == (N!=V) */
32*4882a593Smuzhiyun 0x0A05, /* GT == (!Z && (N==V)) */
33*4882a593Smuzhiyun 0xF5FA, /* LE == (Z || (N!=V)) */
34*4882a593Smuzhiyun 0xFFFF, /* AL always */
35*4882a593Smuzhiyun 0 /* NV */
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * Returns:
40*4882a593Smuzhiyun * ARM_OPCODE_CONDTEST_FAIL - if condition fails
41*4882a593Smuzhiyun * ARM_OPCODE_CONDTEST_PASS - if condition passes (including AL)
42*4882a593Smuzhiyun * ARM_OPCODE_CONDTEST_UNCOND - if NV condition, or separate unconditional
43*4882a593Smuzhiyun * opcode space from v5 onwards
44*4882a593Smuzhiyun *
45*4882a593Smuzhiyun * Code that tests whether a conditional instruction would pass its condition
46*4882a593Smuzhiyun * check should check that return value == ARM_OPCODE_CONDTEST_PASS.
47*4882a593Smuzhiyun *
48*4882a593Smuzhiyun * Code that tests if a condition means that the instruction would be executed
49*4882a593Smuzhiyun * (regardless of conditional or unconditional) should instead check that the
50*4882a593Smuzhiyun * return value != ARM_OPCODE_CONDTEST_FAIL.
51*4882a593Smuzhiyun */
arm_check_condition(u32 opcode,u32 psr)52*4882a593Smuzhiyun asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun u32 cc_bits = opcode >> 28;
55*4882a593Smuzhiyun u32 psr_cond = psr >> 28;
56*4882a593Smuzhiyun unsigned int ret;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
59*4882a593Smuzhiyun if ((cc_map[cc_bits] >> (psr_cond)) & 1)
60*4882a593Smuzhiyun ret = ARM_OPCODE_CONDTEST_PASS;
61*4882a593Smuzhiyun else
62*4882a593Smuzhiyun ret = ARM_OPCODE_CONDTEST_FAIL;
63*4882a593Smuzhiyun } else {
64*4882a593Smuzhiyun ret = ARM_OPCODE_CONDTEST_UNCOND;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return ret;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(arm_check_condition);
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