1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Debugging macro include header 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 Xilinx 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */ 8*4882a593Smuzhiyun#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */ 9*4882a593Smuzhiyun#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 12*4882a593Smuzhiyun#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun#define UART0_PHYS 0xE0000000 15*4882a593Smuzhiyun#define UART0_VIRT 0xF0800000 16*4882a593Smuzhiyun#define UART1_PHYS 0xE0001000 17*4882a593Smuzhiyun#define UART1_VIRT 0xF0801000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1) 20*4882a593Smuzhiyun# define LL_UART_PADDR UART1_PHYS 21*4882a593Smuzhiyun# define LL_UART_VADDR UART1_VIRT 22*4882a593Smuzhiyun#else 23*4882a593Smuzhiyun# define LL_UART_PADDR UART0_PHYS 24*4882a593Smuzhiyun# define LL_UART_VADDR UART0_VIRT 25*4882a593Smuzhiyun#endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun .macro addruart, rp, rv, tmp 28*4882a593Smuzhiyun ldr \rp, =LL_UART_PADDR @ physical 29*4882a593Smuzhiyun ldr \rv, =LL_UART_VADDR @ virtual 30*4882a593Smuzhiyun .endm 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun .macro senduart,rd,rx 33*4882a593Smuzhiyun strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA 34*4882a593Smuzhiyun .endm 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun .macro waituartcts,rd,rx 37*4882a593Smuzhiyun .endm 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun .macro waituarttxrdy,rd,rx 40*4882a593Smuzhiyun1001: ldr \rd, [\rx, #UART_SR_OFFSET] 41*4882a593SmuzhiyunARM_BE8( rev \rd, \rd ) 42*4882a593Smuzhiyun tst \rd, #UART_SR_TXEMPTY 43*4882a593Smuzhiyun beq 1001b 44*4882a593Smuzhiyun .endm 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun .macro busyuart,rd,rx 47*4882a593Smuzhiyun1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register 48*4882a593SmuzhiyunARM_BE8( rev \rd, \rd ) 49*4882a593Smuzhiyun tst \rd, #UART_SR_TXFULL @ 50*4882a593Smuzhiyun bne 1002b @ wait if FIFO is full 51*4882a593Smuzhiyun .endm 52