1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#define VF_UART0_BASE_ADDR 0x40027000 7*4882a593Smuzhiyun#define VF_UART1_BASE_ADDR 0x40028000 8*4882a593Smuzhiyun#define VF_UART2_BASE_ADDR 0x40029000 9*4882a593Smuzhiyun#define VF_UART3_BASE_ADDR 0x4002a000 10*4882a593Smuzhiyun#define VF_UART_BASE_ADDR(n) VF_UART##n##_BASE_ADDR 11*4882a593Smuzhiyun#define VF_UART_BASE(n) VF_UART_BASE_ADDR(n) 12*4882a593Smuzhiyun#define VF_UART_PHYSICAL_BASE VF_UART_BASE(CONFIG_DEBUG_VF_UART_PORT) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun#define VF_UART_VIRTUAL_BASE 0xfe000000 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun .macro addruart, rp, rv, tmp 17*4882a593Smuzhiyun ldr \rp, =VF_UART_PHYSICAL_BASE @ physical 18*4882a593Smuzhiyun and \rv, \rp, #0xffffff @ offset within 16MB section 19*4882a593Smuzhiyun add \rv, \rv, #VF_UART_VIRTUAL_BASE 20*4882a593Smuzhiyun .endm 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun .macro senduart, rd, rx 23*4882a593Smuzhiyun strb \rd, [\rx, #0x7] @ Data Register 24*4882a593Smuzhiyun .endm 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun .macro busyuart, rd, rx 27*4882a593Smuzhiyun1001: ldrb \rd, [\rx, #0x4] @ Status Register 1 28*4882a593Smuzhiyun tst \rd, #1 << 6 @ TC 29*4882a593Smuzhiyun beq 1001b @ wait until transmit done 30*4882a593Smuzhiyun .endm 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun .macro waituartcts,rd,rx 33*4882a593Smuzhiyun .endm 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun .macro waituarttxrdy,rd,rx 36*4882a593Smuzhiyun .endm 37