1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * arch/arm/include/debug/sti.S 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Debugging macro include header 6*4882a593Smuzhiyun * Copyright (C) 2013 STMicroelectronics (R&D) Limited. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#define STIH41X_COMMS_BASE 0xfed00000 10*4882a593Smuzhiyun#define STIH41X_ASC2_BASE (STIH41X_COMMS_BASE+0x32000) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#define STIH41X_SBC_LPM_BASE 0xfe400000 13*4882a593Smuzhiyun#define STIH41X_SBC_COMMS_BASE (STIH41X_SBC_LPM_BASE + 0x100000) 14*4882a593Smuzhiyun#define STIH41X_SBC_ASC1_BASE (STIH41X_SBC_COMMS_BASE + 0x31000) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun#define VIRT_ADDRESS(x) (x - 0x1000000) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun#if IS_ENABLED(CONFIG_STIH41X_DEBUG_ASC2) 20*4882a593Smuzhiyun#define DEBUG_LL_UART_BASE STIH41X_ASC2_BASE 21*4882a593Smuzhiyun#endif 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun#if IS_ENABLED(CONFIG_STIH41X_DEBUG_SBC_ASC1) 24*4882a593Smuzhiyun#define DEBUG_LL_UART_BASE STIH41X_SBC_ASC1_BASE 25*4882a593Smuzhiyun#endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun#ifndef DEBUG_LL_UART_BASE 28*4882a593Smuzhiyun#error "DEBUG UART is not Configured" 29*4882a593Smuzhiyun#endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun#define ASC_TX_BUF_OFF 0x04 32*4882a593Smuzhiyun#define ASC_CTRL_OFF 0x0c 33*4882a593Smuzhiyun#define ASC_STA_OFF 0x14 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun#define ASC_STA_TX_FULL (1<<9) 36*4882a593Smuzhiyun#define ASC_STA_TX_EMPTY (1<<1) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun .macro addruart, rp, rv, tmp 40*4882a593Smuzhiyun ldr \rp, =DEBUG_LL_UART_BASE @ physical base 41*4882a593Smuzhiyun ldr \rv, =VIRT_ADDRESS(DEBUG_LL_UART_BASE) @ virt base 42*4882a593Smuzhiyun .endm 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun .macro senduart,rd,rx 45*4882a593Smuzhiyun strb \rd, [\rx, #ASC_TX_BUF_OFF] 46*4882a593Smuzhiyun .endm 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun .macro waituartcts,rd,rx 49*4882a593Smuzhiyun .endm 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun .macro waituarttxrdy,rd,rx 52*4882a593Smuzhiyun1001: ldr \rd, [\rx, #ASC_STA_OFF] 53*4882a593Smuzhiyun tst \rd, #ASC_STA_TX_FULL 54*4882a593Smuzhiyun bne 1001b 55*4882a593Smuzhiyun .endm 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun .macro busyuart,rd,rx 58*4882a593Smuzhiyun1001: ldr \rd, [\rx, #ASC_STA_OFF] 59*4882a593Smuzhiyun tst \rd, #ASC_STA_TX_EMPTY 60*4882a593Smuzhiyun beq 1001b 61*4882a593Smuzhiyun .endm 62