1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DEBUG_IMX_UART_H 7*4882a593Smuzhiyun #define __DEBUG_IMX_UART_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IMX1_UART1_BASE_ADDR 0x00206000 10*4882a593Smuzhiyun #define IMX1_UART2_BASE_ADDR 0x00207000 11*4882a593Smuzhiyun #define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR 12*4882a593Smuzhiyun #define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define IMX25_UART1_BASE_ADDR 0x43f90000 15*4882a593Smuzhiyun #define IMX25_UART2_BASE_ADDR 0x43f94000 16*4882a593Smuzhiyun #define IMX25_UART3_BASE_ADDR 0x5000c000 17*4882a593Smuzhiyun #define IMX25_UART4_BASE_ADDR 0x50008000 18*4882a593Smuzhiyun #define IMX25_UART5_BASE_ADDR 0x5002c000 19*4882a593Smuzhiyun #define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR 20*4882a593Smuzhiyun #define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define IMX27_UART1_BASE_ADDR 0x1000a000 23*4882a593Smuzhiyun #define IMX27_UART2_BASE_ADDR 0x1000b000 24*4882a593Smuzhiyun #define IMX27_UART3_BASE_ADDR 0x1000c000 25*4882a593Smuzhiyun #define IMX27_UART4_BASE_ADDR 0x1000d000 26*4882a593Smuzhiyun #define IMX27_UART_BASE_ADDR(n) IMX27_UART##n##_BASE_ADDR 27*4882a593Smuzhiyun #define IMX27_UART_BASE(n) IMX27_UART_BASE_ADDR(n) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define IMX31_UART1_BASE_ADDR 0x43f90000 30*4882a593Smuzhiyun #define IMX31_UART2_BASE_ADDR 0x43f94000 31*4882a593Smuzhiyun #define IMX31_UART3_BASE_ADDR 0x5000c000 32*4882a593Smuzhiyun #define IMX31_UART4_BASE_ADDR 0x43fb0000 33*4882a593Smuzhiyun #define IMX31_UART5_BASE_ADDR 0x43fb4000 34*4882a593Smuzhiyun #define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR 35*4882a593Smuzhiyun #define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define IMX35_UART1_BASE_ADDR 0x43f90000 38*4882a593Smuzhiyun #define IMX35_UART2_BASE_ADDR 0x43f94000 39*4882a593Smuzhiyun #define IMX35_UART3_BASE_ADDR 0x5000c000 40*4882a593Smuzhiyun #define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR 41*4882a593Smuzhiyun #define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define IMX50_UART1_BASE_ADDR 0x53fbc000 44*4882a593Smuzhiyun #define IMX50_UART2_BASE_ADDR 0x53fc0000 45*4882a593Smuzhiyun #define IMX50_UART3_BASE_ADDR 0x5000c000 46*4882a593Smuzhiyun #define IMX50_UART4_BASE_ADDR 0x53ff0000 47*4882a593Smuzhiyun #define IMX50_UART5_BASE_ADDR 0x63f90000 48*4882a593Smuzhiyun #define IMX50_UART_BASE_ADDR(n) IMX50_UART##n##_BASE_ADDR 49*4882a593Smuzhiyun #define IMX50_UART_BASE(n) IMX50_UART_BASE_ADDR(n) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define IMX51_UART1_BASE_ADDR 0x73fbc000 52*4882a593Smuzhiyun #define IMX51_UART2_BASE_ADDR 0x73fc0000 53*4882a593Smuzhiyun #define IMX51_UART3_BASE_ADDR 0x7000c000 54*4882a593Smuzhiyun #define IMX51_UART_BASE_ADDR(n) IMX51_UART##n##_BASE_ADDR 55*4882a593Smuzhiyun #define IMX51_UART_BASE(n) IMX51_UART_BASE_ADDR(n) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define IMX53_UART1_BASE_ADDR 0x53fbc000 58*4882a593Smuzhiyun #define IMX53_UART2_BASE_ADDR 0x53fc0000 59*4882a593Smuzhiyun #define IMX53_UART3_BASE_ADDR 0x5000c000 60*4882a593Smuzhiyun #define IMX53_UART4_BASE_ADDR 0x53ff0000 61*4882a593Smuzhiyun #define IMX53_UART5_BASE_ADDR 0x63f90000 62*4882a593Smuzhiyun #define IMX53_UART_BASE_ADDR(n) IMX53_UART##n##_BASE_ADDR 63*4882a593Smuzhiyun #define IMX53_UART_BASE(n) IMX53_UART_BASE_ADDR(n) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define IMX6Q_UART1_BASE_ADDR 0x02020000 66*4882a593Smuzhiyun #define IMX6Q_UART2_BASE_ADDR 0x021e8000 67*4882a593Smuzhiyun #define IMX6Q_UART3_BASE_ADDR 0x021ec000 68*4882a593Smuzhiyun #define IMX6Q_UART4_BASE_ADDR 0x021f0000 69*4882a593Smuzhiyun #define IMX6Q_UART5_BASE_ADDR 0x021f4000 70*4882a593Smuzhiyun #define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR 71*4882a593Smuzhiyun #define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define IMX6SL_UART1_BASE_ADDR 0x02020000 74*4882a593Smuzhiyun #define IMX6SL_UART2_BASE_ADDR 0x02024000 75*4882a593Smuzhiyun #define IMX6SL_UART3_BASE_ADDR 0x02034000 76*4882a593Smuzhiyun #define IMX6SL_UART4_BASE_ADDR 0x02038000 77*4882a593Smuzhiyun #define IMX6SL_UART5_BASE_ADDR 0x02018000 78*4882a593Smuzhiyun #define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR 79*4882a593Smuzhiyun #define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define IMX6SX_UART1_BASE_ADDR 0x02020000 82*4882a593Smuzhiyun #define IMX6SX_UART2_BASE_ADDR 0x021e8000 83*4882a593Smuzhiyun #define IMX6SX_UART3_BASE_ADDR 0x021ec000 84*4882a593Smuzhiyun #define IMX6SX_UART4_BASE_ADDR 0x021f0000 85*4882a593Smuzhiyun #define IMX6SX_UART5_BASE_ADDR 0x021f4000 86*4882a593Smuzhiyun #define IMX6SX_UART6_BASE_ADDR 0x022a0000 87*4882a593Smuzhiyun #define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR 88*4882a593Smuzhiyun #define IMX6SX_UART_BASE(n) IMX6SX_UART_BASE_ADDR(n) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define IMX6UL_UART1_BASE_ADDR 0x02020000 91*4882a593Smuzhiyun #define IMX6UL_UART2_BASE_ADDR 0x021e8000 92*4882a593Smuzhiyun #define IMX6UL_UART3_BASE_ADDR 0x021ec000 93*4882a593Smuzhiyun #define IMX6UL_UART4_BASE_ADDR 0x021f0000 94*4882a593Smuzhiyun #define IMX6UL_UART5_BASE_ADDR 0x021f4000 95*4882a593Smuzhiyun #define IMX6UL_UART6_BASE_ADDR 0x021fc000 96*4882a593Smuzhiyun #define IMX6UL_UART7_BASE_ADDR 0x02018000 97*4882a593Smuzhiyun #define IMX6UL_UART8_BASE_ADDR 0x02024000 98*4882a593Smuzhiyun #define IMX6UL_UART_BASE_ADDR(n) IMX6UL_UART##n##_BASE_ADDR 99*4882a593Smuzhiyun #define IMX6UL_UART_BASE(n) IMX6UL_UART_BASE_ADDR(n) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define IMX7D_UART1_BASE_ADDR 0x30860000 102*4882a593Smuzhiyun #define IMX7D_UART2_BASE_ADDR 0x30890000 103*4882a593Smuzhiyun #define IMX7D_UART3_BASE_ADDR 0x30880000 104*4882a593Smuzhiyun #define IMX7D_UART4_BASE_ADDR 0x30a60000 105*4882a593Smuzhiyun #define IMX7D_UART5_BASE_ADDR 0x30a70000 106*4882a593Smuzhiyun #define IMX7D_UART6_BASE_ADDR 0x30a80000 107*4882a593Smuzhiyun #define IMX7D_UART7_BASE_ADDR 0x30a90000 108*4882a593Smuzhiyun #define IMX7D_UART_BASE_ADDR(n) IMX7D_UART##n##_BASE_ADDR 109*4882a593Smuzhiyun #define IMX7D_UART_BASE(n) IMX7D_UART_BASE_ADDR(n) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT) 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_IMX1_UART 114*4882a593Smuzhiyun #define UART_PADDR IMX_DEBUG_UART_BASE(IMX1) 115*4882a593Smuzhiyun #elif defined(CONFIG_DEBUG_IMX25_UART) 116*4882a593Smuzhiyun #define UART_PADDR IMX_DEBUG_UART_BASE(IMX25) 117*4882a593Smuzhiyun #elif defined(CONFIG_DEBUG_IMX27_UART) 118*4882a593Smuzhiyun #define UART_PADDR IMX_DEBUG_UART_BASE(IMX27) 119*4882a593Smuzhiyun #elif defined(CONFIG_DEBUG_IMX31_UART) 120*4882a593Smuzhiyun #define UART_PADDR IMX_DEBUG_UART_BASE(IMX31) 121*4882a593Smuzhiyun #elif defined(CONFIG_DEBUG_IMX35_UART) 122*4882a593Smuzhiyun #define UART_PADDR IMX_DEBUG_UART_BASE(IMX35) 123*4882a593Smuzhiyun #elif defined(CONFIG_DEBUG_IMX50_UART) 124*4882a593Smuzhiyun #define UART_PADDR IMX_DEBUG_UART_BASE(IMX50) 125*4882a593Smuzhiyun #elif defined(CONFIG_DEBUG_IMX51_UART) 126*4882a593Smuzhiyun #define UART_PADDR IMX_DEBUG_UART_BASE(IMX51) 127*4882a593Smuzhiyun #elif defined(CONFIG_DEBUG_IMX53_UART) 128*4882a593Smuzhiyun #define UART_PADDR IMX_DEBUG_UART_BASE(IMX53) 129*4882a593Smuzhiyun #elif defined(CONFIG_DEBUG_IMX6Q_UART) 130*4882a593Smuzhiyun #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) 131*4882a593Smuzhiyun #elif defined(CONFIG_DEBUG_IMX6SL_UART) 132*4882a593Smuzhiyun #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL) 133*4882a593Smuzhiyun #elif defined(CONFIG_DEBUG_IMX6SX_UART) 134*4882a593Smuzhiyun #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX) 135*4882a593Smuzhiyun #elif defined(CONFIG_DEBUG_IMX6UL_UART) 136*4882a593Smuzhiyun #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6UL) 137*4882a593Smuzhiyun #elif defined(CONFIG_DEBUG_IMX7D_UART) 138*4882a593Smuzhiyun #define UART_PADDR IMX_DEBUG_UART_BASE(IMX7D) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #endif 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #endif /* __DEBUG_IMX_UART_H */ 143