1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * arch/arm/include/debug/icedcc.S 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1994-1999 Russell King 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun @@ debug using ARM EmbeddedICE DCC channel 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun .macro addruart, rp, rv, tmp 11*4882a593Smuzhiyun .endm 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun .macro senduart, rd, rx 16*4882a593Smuzhiyun mcr p14, 0, \rd, c0, c5, 0 17*4882a593Smuzhiyun .endm 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun .macro busyuart, rd, rx 20*4882a593Smuzhiyun1001: 21*4882a593Smuzhiyun mrc p14, 0, \rx, c0, c1, 0 22*4882a593Smuzhiyun tst \rx, #0x20000000 23*4882a593Smuzhiyun beq 1001b 24*4882a593Smuzhiyun .endm 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun .macro waituartcts, rd, rx 27*4882a593Smuzhiyun .endm 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun .macro waituarttxrdy, rd, rx 30*4882a593Smuzhiyun mov \rd, #0x2000000 31*4882a593Smuzhiyun1001: 32*4882a593Smuzhiyun subs \rd, \rd, #1 33*4882a593Smuzhiyun bmi 1002f 34*4882a593Smuzhiyun mrc p14, 0, \rx, c0, c1, 0 35*4882a593Smuzhiyun tst \rx, #0x20000000 36*4882a593Smuzhiyun bne 1001b 37*4882a593Smuzhiyun1002: 38*4882a593Smuzhiyun .endm 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun#elif defined(CONFIG_CPU_XSCALE) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun .macro senduart, rd, rx 43*4882a593Smuzhiyun mcr p14, 0, \rd, c8, c0, 0 44*4882a593Smuzhiyun .endm 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun .macro busyuart, rd, rx 47*4882a593Smuzhiyun1001: 48*4882a593Smuzhiyun mrc p14, 0, \rx, c14, c0, 0 49*4882a593Smuzhiyun tst \rx, #0x10000000 50*4882a593Smuzhiyun beq 1001b 51*4882a593Smuzhiyun .endm 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun .macro waituartcts, rd, rx 54*4882a593Smuzhiyun .endm 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun .macro waituarttxrdy, rd, rx 57*4882a593Smuzhiyun mov \rd, #0x10000000 58*4882a593Smuzhiyun1001: 59*4882a593Smuzhiyun subs \rd, \rd, #1 60*4882a593Smuzhiyun bmi 1002f 61*4882a593Smuzhiyun mrc p14, 0, \rx, c14, c0, 0 62*4882a593Smuzhiyun tst \rx, #0x10000000 63*4882a593Smuzhiyun bne 1001b 64*4882a593Smuzhiyun1002: 65*4882a593Smuzhiyun .endm 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun#else 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun .macro senduart, rd, rx 70*4882a593Smuzhiyun mcr p14, 0, \rd, c1, c0, 0 71*4882a593Smuzhiyun .endm 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun .macro busyuart, rd, rx 74*4882a593Smuzhiyun1001: 75*4882a593Smuzhiyun mrc p14, 0, \rx, c0, c0, 0 76*4882a593Smuzhiyun tst \rx, #2 77*4882a593Smuzhiyun beq 1001b 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun .endm 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun .macro waituartcts, rd, rx 82*4882a593Smuzhiyun .endm 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun .macro waituarttxrdy, rd, rx 85*4882a593Smuzhiyun mov \rd, #0x2000000 86*4882a593Smuzhiyun1001: 87*4882a593Smuzhiyun subs \rd, \rd, #1 88*4882a593Smuzhiyun bmi 1002f 89*4882a593Smuzhiyun mrc p14, 0, \rx, c0, c0, 0 90*4882a593Smuzhiyun tst \rx, #2 91*4882a593Smuzhiyun bne 1001b 92*4882a593Smuzhiyun1002: 93*4882a593Smuzhiyun .endm 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun#endif /* CONFIG_CPU_V6 */ 96