1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2020 ARM Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __ASM_VDSO_CP15_H 6*4882a593Smuzhiyun #define __ASM_VDSO_CP15_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifdef CONFIG_CPU_CP15 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/stringify.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ 15*4882a593Smuzhiyun "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32 16*4882a593Smuzhiyun #define __ACCESS_CP15_64(Op1, CRm) \ 17*4882a593Smuzhiyun "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define __read_sysreg(r, w, c, t) ({ \ 20*4882a593Smuzhiyun t __val; \ 21*4882a593Smuzhiyun asm volatile(r " " c : "=r" (__val)); \ 22*4882a593Smuzhiyun __val; \ 23*4882a593Smuzhiyun }) 24*4882a593Smuzhiyun #define read_sysreg(...) __read_sysreg(__VA_ARGS__) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v))) 27*4882a593Smuzhiyun #define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define BPIALL __ACCESS_CP15(c7, 0, c5, 6) 30*4882a593Smuzhiyun #define ICIALLU __ACCESS_CP15(c7, 0, c5, 0) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define CNTVCT __ACCESS_CP15_64(1, c14) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif /* CONFIG_CPU_CP15 */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #endif /* __ASM_VDSO_CP15_H */ 39