1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/include/asm/pgtable-nommu.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1995-2002 Russell King 6*4882a593Smuzhiyun * Copyright (C) 2004 Hyok S. Choi 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _ASMARM_PGTABLE_NOMMU_H 9*4882a593Smuzhiyun #define _ASMARM_PGTABLE_NOMMU_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/slab.h> 14*4882a593Smuzhiyun #include <asm/processor.h> 15*4882a593Smuzhiyun #include <asm/page.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * Trivial page table functions. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define pgd_present(pgd) (1) 21*4882a593Smuzhiyun #define pgd_none(pgd) (0) 22*4882a593Smuzhiyun #define pgd_bad(pgd) (0) 23*4882a593Smuzhiyun #define pgd_clear(pgdp) 24*4882a593Smuzhiyun #define kern_addr_valid(addr) (1) 25*4882a593Smuzhiyun /* FIXME */ 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * PMD_SHIFT determines the size of the area a second-level page table can map 28*4882a593Smuzhiyun * PGDIR_SHIFT determines what a third-level page table entry can map 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #define PGDIR_SHIFT 21 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 33*4882a593Smuzhiyun #define PGDIR_MASK (~(PGDIR_SIZE-1)) 34*4882a593Smuzhiyun /* FIXME */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define PAGE_NONE __pgprot(0) 37*4882a593Smuzhiyun #define PAGE_SHARED __pgprot(0) 38*4882a593Smuzhiyun #define PAGE_COPY __pgprot(0) 39*4882a593Smuzhiyun #define PAGE_READONLY __pgprot(0) 40*4882a593Smuzhiyun #define PAGE_KERNEL __pgprot(0) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define swapper_pg_dir ((pgd_t *) 0) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun typedef pte_t *pte_addr_t; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * Mark the prot value as uncacheable and unbufferable. 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun #define pgprot_noncached(prot) (prot) 51*4882a593Smuzhiyun #define pgprot_writecombine(prot) (prot) 52*4882a593Smuzhiyun #define pgprot_device(prot) (prot) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * These would be in other places but having them here reduces the diffs. 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun extern unsigned int kobjsize(const void *objp); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * All 32bit addresses are effectively valid for vmalloc... 62*4882a593Smuzhiyun * Sort of meaningless for non-VM targets. 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun #define VMALLOC_START 0UL 65*4882a593Smuzhiyun #define VMALLOC_END 0xffffffffUL 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define FIRST_USER_ADDRESS 0UL 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #else 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* 72*4882a593Smuzhiyun * dummy tlb and user structures. 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun #define v3_tlb_fns (0) 75*4882a593Smuzhiyun #define v4_tlb_fns (0) 76*4882a593Smuzhiyun #define v4wb_tlb_fns (0) 77*4882a593Smuzhiyun #define v4wbi_tlb_fns (0) 78*4882a593Smuzhiyun #define v6wbi_tlb_fns (0) 79*4882a593Smuzhiyun #define v7wbi_tlb_fns (0) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define v3_user_fns (0) 82*4882a593Smuzhiyun #define v4_user_fns (0) 83*4882a593Smuzhiyun #define v4_mc_user_fns (0) 84*4882a593Smuzhiyun #define v4wb_user_fns (0) 85*4882a593Smuzhiyun #define v4wt_user_fns (0) 86*4882a593Smuzhiyun #define v6_user_fns (0) 87*4882a593Smuzhiyun #define xscale_mc_user_fns (0) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif /*__ASSEMBLY__*/ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif /* _ASMARM_PGTABLE_H */ 92