1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/include/asm/pgtable-3level-hwdef.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 ARM Ltd. 6*4882a593Smuzhiyun * Author: Catalin Marinas <catalin.marinas@arm.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _ASM_PGTABLE_3LEVEL_HWDEF_H 9*4882a593Smuzhiyun #define _ASM_PGTABLE_3LEVEL_HWDEF_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Hardware page table definitions. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * + Level 1/2 descriptor 15*4882a593Smuzhiyun * - common 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 18*4882a593Smuzhiyun #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 19*4882a593Smuzhiyun #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 20*4882a593Smuzhiyun #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 21*4882a593Smuzhiyun #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 22*4882a593Smuzhiyun #define PMD_BIT4 (_AT(pmdval_t, 0)) 23*4882a593Smuzhiyun #define PMD_DOMAIN(x) (_AT(pmdval_t, 0)) 24*4882a593Smuzhiyun #define PMD_APTABLE_SHIFT (61) 25*4882a593Smuzhiyun #define PMD_APTABLE (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT) 26*4882a593Smuzhiyun #define PMD_PXNTABLE (_AT(pgdval_t, 1) << 59) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * - section 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun #define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2) 32*4882a593Smuzhiyun #define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) 33*4882a593Smuzhiyun #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 34*4882a593Smuzhiyun #define PMD_SECT_AP2 (_AT(pmdval_t, 1) << 7) /* read only */ 35*4882a593Smuzhiyun #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 36*4882a593Smuzhiyun #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 37*4882a593Smuzhiyun #define PMD_SECT_nG (_AT(pmdval_t, 1) << 11) 38*4882a593Smuzhiyun #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 39*4882a593Smuzhiyun #define PMD_SECT_XN (_AT(pmdval_t, 1) << 54) 40*4882a593Smuzhiyun #define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0)) 41*4882a593Smuzhiyun #define PMD_SECT_AP_READ (_AT(pmdval_t, 0)) 42*4882a593Smuzhiyun #define PMD_SECT_AP1 (_AT(pmdval_t, 1) << 6) 43*4882a593Smuzhiyun #define PMD_SECT_TEX(x) (_AT(pmdval_t, 0)) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun #define PMD_SECT_UNCACHED (_AT(pmdval_t, 0) << 2) /* strongly ordered */ 49*4882a593Smuzhiyun #define PMD_SECT_BUFFERED (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */ 50*4882a593Smuzhiyun #define PMD_SECT_WT (_AT(pmdval_t, 2) << 2) /* normal inner write-through */ 51*4882a593Smuzhiyun #define PMD_SECT_WB (_AT(pmdval_t, 3) << 2) /* normal inner write-back */ 52*4882a593Smuzhiyun #define PMD_SECT_WBWA (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */ 53*4882a593Smuzhiyun #define PMD_SECT_CACHE_MASK (_AT(pmdval_t, 7) << 2) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * + Level 3 descriptor (PTE) 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 59*4882a593Smuzhiyun #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 60*4882a593Smuzhiyun #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 61*4882a593Smuzhiyun #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 62*4882a593Smuzhiyun #define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ 63*4882a593Smuzhiyun #define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ 64*4882a593Smuzhiyun #define PTE_AP2 (_AT(pteval_t, 1) << 7) /* AP[2] */ 65*4882a593Smuzhiyun #define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 66*4882a593Smuzhiyun #define PTE_EXT_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 67*4882a593Smuzhiyun #define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* nG */ 68*4882a593Smuzhiyun #define PTE_EXT_PXN (_AT(pteval_t, 1) << 53) /* PXN */ 69*4882a593Smuzhiyun #define PTE_EXT_XN (_AT(pteval_t, 1) << 54) /* XN */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* 72*4882a593Smuzhiyun * 40-bit physical address supported. 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun #define PHYS_MASK_SHIFT (40) 75*4882a593Smuzhiyun #define PHYS_MASK ((1ULL << PHYS_MASK_SHIFT) - 1) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * TTBR0/TTBR1 split (PAGE_OFFSET): 79*4882a593Smuzhiyun * 0x40000000: T0SZ = 2, T1SZ = 0 (not used) 80*4882a593Smuzhiyun * 0x80000000: T0SZ = 0, T1SZ = 1 81*4882a593Smuzhiyun * 0xc0000000: T0SZ = 0, T1SZ = 2 82*4882a593Smuzhiyun * 83*4882a593Smuzhiyun * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise 84*4882a593Smuzhiyun * booting secondary CPUs would end up using TTBR1 for the identity 85*4882a593Smuzhiyun * mapping set up in TTBR0. 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun #if defined CONFIG_VMSPLIT_2G 88*4882a593Smuzhiyun #define TTBR1_OFFSET 16 /* skip two L1 entries */ 89*4882a593Smuzhiyun #elif defined CONFIG_VMSPLIT_3G 90*4882a593Smuzhiyun #define TTBR1_OFFSET (4096 * (1 + 3)) /* only L2, skip pgd + 3*pmd */ 91*4882a593Smuzhiyun #else 92*4882a593Smuzhiyun #define TTBR1_OFFSET 0 93*4882a593Smuzhiyun #endif 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define TTBR1_SIZE (((PAGE_OFFSET >> 30) - 1) << 16) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #endif 98