1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/include/asm/outercache.h
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2010 ARM Ltd.
6*4882a593Smuzhiyun * Written by Catalin Marinas <catalin.marinas@arm.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __ASM_OUTERCACHE_H
10*4882a593Smuzhiyun #define __ASM_OUTERCACHE_H
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/types.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun struct l2x0_regs;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct outer_cache_fns {
17*4882a593Smuzhiyun void (*inv_range)(unsigned long, unsigned long);
18*4882a593Smuzhiyun void (*clean_range)(unsigned long, unsigned long);
19*4882a593Smuzhiyun void (*flush_range)(unsigned long, unsigned long);
20*4882a593Smuzhiyun void (*flush_all)(void);
21*4882a593Smuzhiyun void (*disable)(void);
22*4882a593Smuzhiyun #ifdef CONFIG_OUTER_CACHE_SYNC
23*4882a593Smuzhiyun void (*sync)(void);
24*4882a593Smuzhiyun #endif
25*4882a593Smuzhiyun void (*resume)(void);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* This is an ARM L2C thing */
28*4882a593Smuzhiyun void (*write_sec)(unsigned long, unsigned);
29*4882a593Smuzhiyun void (*configure)(const struct l2x0_regs *);
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun extern struct outer_cache_fns outer_cache;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #ifdef CONFIG_OUTER_CACHE
35*4882a593Smuzhiyun /**
36*4882a593Smuzhiyun * outer_inv_range - invalidate range of outer cache lines
37*4882a593Smuzhiyun * @start: starting physical address, inclusive
38*4882a593Smuzhiyun * @end: end physical address, exclusive
39*4882a593Smuzhiyun */
outer_inv_range(phys_addr_t start,phys_addr_t end)40*4882a593Smuzhiyun static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun if (outer_cache.inv_range)
43*4882a593Smuzhiyun outer_cache.inv_range(start, end);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /**
47*4882a593Smuzhiyun * outer_clean_range - clean dirty outer cache lines
48*4882a593Smuzhiyun * @start: starting physical address, inclusive
49*4882a593Smuzhiyun * @end: end physical address, exclusive
50*4882a593Smuzhiyun */
outer_clean_range(phys_addr_t start,phys_addr_t end)51*4882a593Smuzhiyun static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun if (outer_cache.clean_range)
54*4882a593Smuzhiyun outer_cache.clean_range(start, end);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /**
58*4882a593Smuzhiyun * outer_flush_range - clean and invalidate outer cache lines
59*4882a593Smuzhiyun * @start: starting physical address, inclusive
60*4882a593Smuzhiyun * @end: end physical address, exclusive
61*4882a593Smuzhiyun */
outer_flush_range(phys_addr_t start,phys_addr_t end)62*4882a593Smuzhiyun static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun if (outer_cache.flush_range)
65*4882a593Smuzhiyun outer_cache.flush_range(start, end);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /**
69*4882a593Smuzhiyun * outer_flush_all - clean and invalidate all cache lines in the outer cache
70*4882a593Smuzhiyun *
71*4882a593Smuzhiyun * Note: depending on implementation, this may not be atomic - it must
72*4882a593Smuzhiyun * only be called with interrupts disabled and no other active outer
73*4882a593Smuzhiyun * cache masters.
74*4882a593Smuzhiyun *
75*4882a593Smuzhiyun * It is intended that this function is only used by implementations
76*4882a593Smuzhiyun * needing to override the outer_cache.disable() method due to security.
77*4882a593Smuzhiyun * (Some implementations perform this as a clean followed by an invalidate.)
78*4882a593Smuzhiyun */
outer_flush_all(void)79*4882a593Smuzhiyun static inline void outer_flush_all(void)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun if (outer_cache.flush_all)
82*4882a593Smuzhiyun outer_cache.flush_all();
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /**
86*4882a593Smuzhiyun * outer_disable - clean, invalidate and disable the outer cache
87*4882a593Smuzhiyun *
88*4882a593Smuzhiyun * Disable the outer cache, ensuring that any data contained in the outer
89*4882a593Smuzhiyun * cache is pushed out to lower levels of system memory. The note and
90*4882a593Smuzhiyun * conditions above concerning outer_flush_all() applies here.
91*4882a593Smuzhiyun */
92*4882a593Smuzhiyun extern void outer_disable(void);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /**
95*4882a593Smuzhiyun * outer_resume - restore the cache configuration and re-enable outer cache
96*4882a593Smuzhiyun *
97*4882a593Smuzhiyun * Restore any configuration that the cache had when previously enabled,
98*4882a593Smuzhiyun * and re-enable the outer cache.
99*4882a593Smuzhiyun */
outer_resume(void)100*4882a593Smuzhiyun static inline void outer_resume(void)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun if (outer_cache.resume)
103*4882a593Smuzhiyun outer_cache.resume();
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun #else
107*4882a593Smuzhiyun
outer_inv_range(phys_addr_t start,phys_addr_t end)108*4882a593Smuzhiyun static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
109*4882a593Smuzhiyun { }
outer_clean_range(phys_addr_t start,phys_addr_t end)110*4882a593Smuzhiyun static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
111*4882a593Smuzhiyun { }
outer_flush_range(phys_addr_t start,phys_addr_t end)112*4882a593Smuzhiyun static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
113*4882a593Smuzhiyun { }
outer_flush_all(void)114*4882a593Smuzhiyun static inline void outer_flush_all(void) { }
outer_disable(void)115*4882a593Smuzhiyun static inline void outer_disable(void) { }
outer_resume(void)116*4882a593Smuzhiyun static inline void outer_resume(void) { }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun #endif
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun #endif /* __ASM_OUTERCACHE_H */
121