1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ARM_MPU_H 3*4882a593Smuzhiyun #define __ARM_MPU_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* MPUIR layout */ 6*4882a593Smuzhiyun #define MPUIR_nU 1 7*4882a593Smuzhiyun #define MPUIR_DREGION 8 8*4882a593Smuzhiyun #define MPUIR_IREGION 16 9*4882a593Smuzhiyun #define MPUIR_DREGION_SZMASK (0xFF << MPUIR_DREGION) 10*4882a593Smuzhiyun #define MPUIR_IREGION_SZMASK (0xFF << MPUIR_IREGION) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* ID_MMFR0 data relevant to MPU */ 13*4882a593Smuzhiyun #define MMFR0_PMSA (0xF << 4) 14*4882a593Smuzhiyun #define MMFR0_PMSAv7 (3 << 4) 15*4882a593Smuzhiyun #define MMFR0_PMSAv8 (4 << 4) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* MPU D/I Size Register fields */ 18*4882a593Smuzhiyun #define PMSAv7_RSR_SZ 1 19*4882a593Smuzhiyun #define PMSAv7_RSR_EN 0 20*4882a593Smuzhiyun #define PMSAv7_RSR_SD 8 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Number of subregions (SD) */ 23*4882a593Smuzhiyun #define PMSAv7_NR_SUBREGS 8 24*4882a593Smuzhiyun #define PMSAv7_MIN_SUBREG_SIZE 256 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* The D/I RSR value for an enabled region spanning the whole of memory */ 27*4882a593Smuzhiyun #define PMSAv7_RSR_ALL_MEM 63 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Individual bits in the DR/IR ACR */ 30*4882a593Smuzhiyun #define PMSAv7_ACR_XN (1 << 12) 31*4882a593Smuzhiyun #define PMSAv7_ACR_SHARED (1 << 2) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* C, B and TEX[2:0] bits only have semantic meanings when grouped */ 34*4882a593Smuzhiyun #define PMSAv7_RGN_CACHEABLE 0xB 35*4882a593Smuzhiyun #define PMSAv7_RGN_SHARED_CACHEABLE (PMSAv7_RGN_CACHEABLE | PMSAv7_ACR_SHARED) 36*4882a593Smuzhiyun #define PMSAv7_RGN_STRONGLY_ORDERED 0 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Main region should only be shared for SMP */ 39*4882a593Smuzhiyun #ifdef CONFIG_SMP 40*4882a593Smuzhiyun #define PMSAv7_RGN_NORMAL (PMSAv7_RGN_CACHEABLE | PMSAv7_ACR_SHARED) 41*4882a593Smuzhiyun #else 42*4882a593Smuzhiyun #define PMSAv7_RGN_NORMAL PMSAv7_RGN_CACHEABLE 43*4882a593Smuzhiyun #endif 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Access permission bits of ACR (only define those that we use)*/ 46*4882a593Smuzhiyun #define PMSAv7_AP_PL1RO_PL0NA (0x5 << 8) 47*4882a593Smuzhiyun #define PMSAv7_AP_PL1RW_PL0RW (0x3 << 8) 48*4882a593Smuzhiyun #define PMSAv7_AP_PL1RW_PL0R0 (0x2 << 8) 49*4882a593Smuzhiyun #define PMSAv7_AP_PL1RW_PL0NA (0x1 << 8) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define PMSAv8_BAR_XN 1 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define PMSAv8_LAR_EN 1 54*4882a593Smuzhiyun #define PMSAv8_LAR_IDX(n) (((n) & 0x7) << 1) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define PMSAv8_AP_PL1RW_PL0NA (0 << 1) 58*4882a593Smuzhiyun #define PMSAv8_AP_PL1RW_PL0RW (1 << 1) 59*4882a593Smuzhiyun #define PMSAv8_AP_PL1RO_PL0RO (3 << 1) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #ifdef CONFIG_SMP 62*4882a593Smuzhiyun #define PMSAv8_RGN_SHARED (3 << 3) // inner sharable 63*4882a593Smuzhiyun #else 64*4882a593Smuzhiyun #define PMSAv8_RGN_SHARED (0 << 3) 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define PMSAv8_RGN_DEVICE_nGnRnE 0 68*4882a593Smuzhiyun #define PMSAv8_RGN_NORMAL 1 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define PMSAv8_MAIR(attr, mt) ((attr) << ((mt) * 8)) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #ifdef CONFIG_CPU_V7M 73*4882a593Smuzhiyun #define PMSAv8_MINALIGN 32 74*4882a593Smuzhiyun #else 75*4882a593Smuzhiyun #define PMSAv8_MINALIGN 64 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* For minimal static MPU region configurations */ 79*4882a593Smuzhiyun #define PMSAv7_PROBE_REGION 0 80*4882a593Smuzhiyun #define PMSAv7_BG_REGION 1 81*4882a593Smuzhiyun #define PMSAv7_RAM_REGION 2 82*4882a593Smuzhiyun #define PMSAv7_ROM_REGION 3 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* Fixed for PMSAv8 only */ 85*4882a593Smuzhiyun #define PMSAv8_XIP_REGION 0 86*4882a593Smuzhiyun #define PMSAv8_KERNEL_REGION 1 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Maximum number of regions Linux is interested in */ 89*4882a593Smuzhiyun #define MPU_MAX_REGIONS 16 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define PMSAv7_DATA_SIDE 0 92*4882a593Smuzhiyun #define PMSAv7_INSTR_SIDE 1 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun struct mpu_rgn { 97*4882a593Smuzhiyun /* Assume same attributes for d/i-side */ 98*4882a593Smuzhiyun union { 99*4882a593Smuzhiyun u32 drbar; /* PMSAv7 */ 100*4882a593Smuzhiyun u32 prbar; /* PMSAv8 */ 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun union { 103*4882a593Smuzhiyun u32 drsr; /* PMSAv7 */ 104*4882a593Smuzhiyun u32 prlar; /* PMSAv8 */ 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun union { 107*4882a593Smuzhiyun u32 dracr; /* PMSAv7 */ 108*4882a593Smuzhiyun u32 unused; /* not used in PMSAv8 */ 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun struct mpu_rgn_info { 113*4882a593Smuzhiyun unsigned int used; 114*4882a593Smuzhiyun struct mpu_rgn rgns[MPU_MAX_REGIONS]; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun extern struct mpu_rgn_info mpu_rgn_info; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #ifdef CONFIG_ARM_MPU 119*4882a593Smuzhiyun extern void __init pmsav7_adjust_lowmem_bounds(void); 120*4882a593Smuzhiyun extern void __init pmsav8_adjust_lowmem_bounds(void); 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun extern void __init pmsav7_setup(void); 123*4882a593Smuzhiyun extern void __init pmsav8_setup(void); 124*4882a593Smuzhiyun #else pmsav7_adjust_lowmem_bounds(void)125*4882a593Smuzhiyunstatic inline void pmsav7_adjust_lowmem_bounds(void) {}; pmsav8_adjust_lowmem_bounds(void)126*4882a593Smuzhiyunstatic inline void pmsav8_adjust_lowmem_bounds(void) {}; pmsav7_setup(void)127*4882a593Smuzhiyunstatic inline void pmsav7_setup(void) {}; pmsav8_setup(void)128*4882a593Smuzhiyunstatic inline void pmsav8_setup(void) {}; 129*4882a593Smuzhiyun #endif 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #endif 134