1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/include/asm/mach/pci.h
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2000 Russell King
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef __ASM_MACH_PCI_H
9*4882a593Smuzhiyun #define __ASM_MACH_PCI_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/ioport.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun struct pci_sys_data;
14*4882a593Smuzhiyun struct pci_ops;
15*4882a593Smuzhiyun struct pci_bus;
16*4882a593Smuzhiyun struct pci_host_bridge;
17*4882a593Smuzhiyun struct device;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct hw_pci {
20*4882a593Smuzhiyun struct pci_ops *ops;
21*4882a593Smuzhiyun int nr_controllers;
22*4882a593Smuzhiyun void **private_data;
23*4882a593Smuzhiyun int (*setup)(int nr, struct pci_sys_data *);
24*4882a593Smuzhiyun int (*scan)(int nr, struct pci_host_bridge *);
25*4882a593Smuzhiyun void (*preinit)(void);
26*4882a593Smuzhiyun void (*postinit)(void);
27*4882a593Smuzhiyun u8 (*swizzle)(struct pci_dev *dev, u8 *pin);
28*4882a593Smuzhiyun int (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * Per-controller structure
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun struct pci_sys_data {
35*4882a593Smuzhiyun struct list_head node;
36*4882a593Smuzhiyun int busnr; /* primary bus number */
37*4882a593Smuzhiyun u64 mem_offset; /* bus->cpu memory mapping offset */
38*4882a593Smuzhiyun unsigned long io_offset; /* bus->cpu IO mapping offset */
39*4882a593Smuzhiyun struct pci_bus *bus; /* PCI bus */
40*4882a593Smuzhiyun struct list_head resources; /* root bus resources (apertures) */
41*4882a593Smuzhiyun struct resource io_res;
42*4882a593Smuzhiyun char io_res_name[12];
43*4882a593Smuzhiyun /* Bridge swizzling */
44*4882a593Smuzhiyun u8 (*swizzle)(struct pci_dev *, u8 *);
45*4882a593Smuzhiyun /* IRQ mapping */
46*4882a593Smuzhiyun int (*map_irq)(const struct pci_dev *, u8, u8);
47*4882a593Smuzhiyun void *private_data; /* platform controller private data */
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /*
51*4882a593Smuzhiyun * Call this with your hw_pci struct to initialise the PCI system.
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun void pci_common_init_dev(struct device *, struct hw_pci *);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * Compatibility wrapper for older platforms that do not care about
57*4882a593Smuzhiyun * passing the parent device.
58*4882a593Smuzhiyun */
pci_common_init(struct hw_pci * hw)59*4882a593Smuzhiyun static inline void pci_common_init(struct hw_pci *hw)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun pci_common_init_dev(NULL, hw);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /*
65*4882a593Smuzhiyun * Setup early fixed I/O mapping.
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun #if defined(CONFIG_PCI)
68*4882a593Smuzhiyun extern void pci_map_io_early(unsigned long pfn);
69*4882a593Smuzhiyun #else
pci_map_io_early(unsigned long pfn)70*4882a593Smuzhiyun static inline void pci_map_io_early(unsigned long pfn) {}
71*4882a593Smuzhiyun #endif
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun * PCI controllers
75*4882a593Smuzhiyun */
76*4882a593Smuzhiyun extern struct pci_ops iop3xx_ops;
77*4882a593Smuzhiyun extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
78*4882a593Smuzhiyun extern void iop3xx_pci_preinit(void);
79*4882a593Smuzhiyun extern void iop3xx_pci_preinit_cond(void);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun extern struct pci_ops dc21285_ops;
82*4882a593Smuzhiyun extern int dc21285_setup(int nr, struct pci_sys_data *);
83*4882a593Smuzhiyun extern void dc21285_preinit(void);
84*4882a593Smuzhiyun extern void dc21285_postinit(void);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #endif /* __ASM_MACH_PCI_H */
87