1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef __ASM_ARM_IRQFLAGS_H
3*4882a593Smuzhiyun #define __ASM_ARM_IRQFLAGS_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #ifdef __KERNEL__
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <asm/ptrace.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun * CPU interrupt mask handling.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun #ifdef CONFIG_CPU_V7M
13*4882a593Smuzhiyun #define IRQMASK_REG_NAME_R "primask"
14*4882a593Smuzhiyun #define IRQMASK_REG_NAME_W "primask"
15*4882a593Smuzhiyun #define IRQMASK_I_BIT 1
16*4882a593Smuzhiyun #else
17*4882a593Smuzhiyun #define IRQMASK_REG_NAME_R "cpsr"
18*4882a593Smuzhiyun #define IRQMASK_REG_NAME_W "cpsr_c"
19*4882a593Smuzhiyun #define IRQMASK_I_BIT PSR_I_BIT
20*4882a593Smuzhiyun #endif
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #if __LINUX_ARM_ARCH__ >= 6
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define arch_local_irq_save arch_local_irq_save
arch_local_irq_save(void)25*4882a593Smuzhiyun static inline unsigned long arch_local_irq_save(void)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun unsigned long flags;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun asm volatile(
30*4882a593Smuzhiyun " mrs %0, " IRQMASK_REG_NAME_R " @ arch_local_irq_save\n"
31*4882a593Smuzhiyun " cpsid i"
32*4882a593Smuzhiyun : "=r" (flags) : : "memory", "cc");
33*4882a593Smuzhiyun return flags;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define arch_local_irq_enable arch_local_irq_enable
arch_local_irq_enable(void)37*4882a593Smuzhiyun static inline void arch_local_irq_enable(void)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun asm volatile(
40*4882a593Smuzhiyun " cpsie i @ arch_local_irq_enable"
41*4882a593Smuzhiyun :
42*4882a593Smuzhiyun :
43*4882a593Smuzhiyun : "memory", "cc");
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define arch_local_irq_disable arch_local_irq_disable
arch_local_irq_disable(void)47*4882a593Smuzhiyun static inline void arch_local_irq_disable(void)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun asm volatile(
50*4882a593Smuzhiyun " cpsid i @ arch_local_irq_disable"
51*4882a593Smuzhiyun :
52*4882a593Smuzhiyun :
53*4882a593Smuzhiyun : "memory", "cc");
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc")
57*4882a593Smuzhiyun #define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc")
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #ifndef CONFIG_CPU_V7M
60*4882a593Smuzhiyun #define local_abt_enable() __asm__("cpsie a @ __sta" : : : "memory", "cc")
61*4882a593Smuzhiyun #define local_abt_disable() __asm__("cpsid a @ __cla" : : : "memory", "cc")
62*4882a593Smuzhiyun #else
63*4882a593Smuzhiyun #define local_abt_enable() do { } while (0)
64*4882a593Smuzhiyun #define local_abt_disable() do { } while (0)
65*4882a593Smuzhiyun #endif
66*4882a593Smuzhiyun #else
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /*
69*4882a593Smuzhiyun * Save the current interrupt enable state & disable IRQs
70*4882a593Smuzhiyun */
71*4882a593Smuzhiyun #define arch_local_irq_save arch_local_irq_save
arch_local_irq_save(void)72*4882a593Smuzhiyun static inline unsigned long arch_local_irq_save(void)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun unsigned long flags, temp;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun asm volatile(
77*4882a593Smuzhiyun " mrs %0, cpsr @ arch_local_irq_save\n"
78*4882a593Smuzhiyun " orr %1, %0, #128\n"
79*4882a593Smuzhiyun " msr cpsr_c, %1"
80*4882a593Smuzhiyun : "=r" (flags), "=r" (temp)
81*4882a593Smuzhiyun :
82*4882a593Smuzhiyun : "memory", "cc");
83*4882a593Smuzhiyun return flags;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /*
87*4882a593Smuzhiyun * Enable IRQs
88*4882a593Smuzhiyun */
89*4882a593Smuzhiyun #define arch_local_irq_enable arch_local_irq_enable
arch_local_irq_enable(void)90*4882a593Smuzhiyun static inline void arch_local_irq_enable(void)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun unsigned long temp;
93*4882a593Smuzhiyun asm volatile(
94*4882a593Smuzhiyun " mrs %0, cpsr @ arch_local_irq_enable\n"
95*4882a593Smuzhiyun " bic %0, %0, #128\n"
96*4882a593Smuzhiyun " msr cpsr_c, %0"
97*4882a593Smuzhiyun : "=r" (temp)
98*4882a593Smuzhiyun :
99*4882a593Smuzhiyun : "memory", "cc");
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /*
103*4882a593Smuzhiyun * Disable IRQs
104*4882a593Smuzhiyun */
105*4882a593Smuzhiyun #define arch_local_irq_disable arch_local_irq_disable
arch_local_irq_disable(void)106*4882a593Smuzhiyun static inline void arch_local_irq_disable(void)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun unsigned long temp;
109*4882a593Smuzhiyun asm volatile(
110*4882a593Smuzhiyun " mrs %0, cpsr @ arch_local_irq_disable\n"
111*4882a593Smuzhiyun " orr %0, %0, #128\n"
112*4882a593Smuzhiyun " msr cpsr_c, %0"
113*4882a593Smuzhiyun : "=r" (temp)
114*4882a593Smuzhiyun :
115*4882a593Smuzhiyun : "memory", "cc");
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /*
119*4882a593Smuzhiyun * Enable FIQs
120*4882a593Smuzhiyun */
121*4882a593Smuzhiyun #define local_fiq_enable() \
122*4882a593Smuzhiyun ({ \
123*4882a593Smuzhiyun unsigned long temp; \
124*4882a593Smuzhiyun __asm__ __volatile__( \
125*4882a593Smuzhiyun "mrs %0, cpsr @ stf\n" \
126*4882a593Smuzhiyun " bic %0, %0, #64\n" \
127*4882a593Smuzhiyun " msr cpsr_c, %0" \
128*4882a593Smuzhiyun : "=r" (temp) \
129*4882a593Smuzhiyun : \
130*4882a593Smuzhiyun : "memory", "cc"); \
131*4882a593Smuzhiyun })
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /*
134*4882a593Smuzhiyun * Disable FIQs
135*4882a593Smuzhiyun */
136*4882a593Smuzhiyun #define local_fiq_disable() \
137*4882a593Smuzhiyun ({ \
138*4882a593Smuzhiyun unsigned long temp; \
139*4882a593Smuzhiyun __asm__ __volatile__( \
140*4882a593Smuzhiyun "mrs %0, cpsr @ clf\n" \
141*4882a593Smuzhiyun " orr %0, %0, #64\n" \
142*4882a593Smuzhiyun " msr cpsr_c, %0" \
143*4882a593Smuzhiyun : "=r" (temp) \
144*4882a593Smuzhiyun : \
145*4882a593Smuzhiyun : "memory", "cc"); \
146*4882a593Smuzhiyun })
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun #define local_abt_enable() do { } while (0)
149*4882a593Smuzhiyun #define local_abt_disable() do { } while (0)
150*4882a593Smuzhiyun #endif
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun /*
153*4882a593Smuzhiyun * Save the current interrupt enable state.
154*4882a593Smuzhiyun */
155*4882a593Smuzhiyun #define arch_local_save_flags arch_local_save_flags
arch_local_save_flags(void)156*4882a593Smuzhiyun static inline unsigned long arch_local_save_flags(void)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun unsigned long flags;
159*4882a593Smuzhiyun asm volatile(
160*4882a593Smuzhiyun " mrs %0, " IRQMASK_REG_NAME_R " @ local_save_flags"
161*4882a593Smuzhiyun : "=r" (flags) : : "memory", "cc");
162*4882a593Smuzhiyun return flags;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /*
166*4882a593Smuzhiyun * restore saved IRQ & FIQ state
167*4882a593Smuzhiyun */
168*4882a593Smuzhiyun #define arch_local_irq_restore arch_local_irq_restore
arch_local_irq_restore(unsigned long flags)169*4882a593Smuzhiyun static inline void arch_local_irq_restore(unsigned long flags)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun asm volatile(
172*4882a593Smuzhiyun " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore"
173*4882a593Smuzhiyun :
174*4882a593Smuzhiyun : "r" (flags)
175*4882a593Smuzhiyun : "memory", "cc");
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun #define arch_irqs_disabled_flags arch_irqs_disabled_flags
arch_irqs_disabled_flags(unsigned long flags)179*4882a593Smuzhiyun static inline int arch_irqs_disabled_flags(unsigned long flags)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun return flags & IRQMASK_I_BIT;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun #include <asm-generic/irqflags.h>
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun #endif /* ifdef __KERNEL__ */
187*4882a593Smuzhiyun #endif /* ifndef __ASM_ARM_IRQFLAGS_H */
188