1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef _ARM_HW_BREAKPOINT_H
3*4882a593Smuzhiyun #define _ARM_HW_BREAKPOINT_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #ifdef __KERNEL__
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun struct task_struct;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifdef CONFIG_HAVE_HW_BREAKPOINT
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun struct arch_hw_breakpoint_ctrl {
12*4882a593Smuzhiyun u32 __reserved : 9,
13*4882a593Smuzhiyun mismatch : 1,
14*4882a593Smuzhiyun : 9,
15*4882a593Smuzhiyun len : 8,
16*4882a593Smuzhiyun type : 2,
17*4882a593Smuzhiyun privilege : 2,
18*4882a593Smuzhiyun enabled : 1;
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct arch_hw_breakpoint {
22*4882a593Smuzhiyun u32 address;
23*4882a593Smuzhiyun u32 trigger;
24*4882a593Smuzhiyun struct arch_hw_breakpoint_ctrl step_ctrl;
25*4882a593Smuzhiyun struct arch_hw_breakpoint_ctrl ctrl;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)28*4882a593Smuzhiyun static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) |
31*4882a593Smuzhiyun (ctrl.privilege << 1) | ctrl.enabled;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
decode_ctrl_reg(u32 reg,struct arch_hw_breakpoint_ctrl * ctrl)34*4882a593Smuzhiyun static inline void decode_ctrl_reg(u32 reg,
35*4882a593Smuzhiyun struct arch_hw_breakpoint_ctrl *ctrl)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun ctrl->enabled = reg & 0x1;
38*4882a593Smuzhiyun reg >>= 1;
39*4882a593Smuzhiyun ctrl->privilege = reg & 0x3;
40*4882a593Smuzhiyun reg >>= 2;
41*4882a593Smuzhiyun ctrl->type = reg & 0x3;
42*4882a593Smuzhiyun reg >>= 2;
43*4882a593Smuzhiyun ctrl->len = reg & 0xff;
44*4882a593Smuzhiyun reg >>= 17;
45*4882a593Smuzhiyun ctrl->mismatch = reg & 0x1;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Debug architecture numbers. */
49*4882a593Smuzhiyun #define ARM_DEBUG_ARCH_RESERVED 0 /* In case of ptrace ABI updates. */
50*4882a593Smuzhiyun #define ARM_DEBUG_ARCH_V6 1
51*4882a593Smuzhiyun #define ARM_DEBUG_ARCH_V6_1 2
52*4882a593Smuzhiyun #define ARM_DEBUG_ARCH_V7_ECP14 3
53*4882a593Smuzhiyun #define ARM_DEBUG_ARCH_V7_MM 4
54*4882a593Smuzhiyun #define ARM_DEBUG_ARCH_V7_1 5
55*4882a593Smuzhiyun #define ARM_DEBUG_ARCH_V8 6
56*4882a593Smuzhiyun #define ARM_DEBUG_ARCH_V8_1 7
57*4882a593Smuzhiyun #define ARM_DEBUG_ARCH_V8_2 8
58*4882a593Smuzhiyun #define ARM_DEBUG_ARCH_V8_4 9
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Breakpoint */
61*4882a593Smuzhiyun #define ARM_BREAKPOINT_EXECUTE 0
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Watchpoints */
64*4882a593Smuzhiyun #define ARM_BREAKPOINT_LOAD 1
65*4882a593Smuzhiyun #define ARM_BREAKPOINT_STORE 2
66*4882a593Smuzhiyun #define ARM_FSR_ACCESS_MASK (1 << 11)
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* Privilege Levels */
69*4882a593Smuzhiyun #define ARM_BREAKPOINT_PRIV 1
70*4882a593Smuzhiyun #define ARM_BREAKPOINT_USER 2
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Lengths */
73*4882a593Smuzhiyun #define ARM_BREAKPOINT_LEN_1 0x1
74*4882a593Smuzhiyun #define ARM_BREAKPOINT_LEN_2 0x3
75*4882a593Smuzhiyun #define ARM_BREAKPOINT_LEN_4 0xf
76*4882a593Smuzhiyun #define ARM_BREAKPOINT_LEN_8 0xff
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* Limits */
79*4882a593Smuzhiyun #define ARM_MAX_BRP 16
80*4882a593Smuzhiyun #define ARM_MAX_WRP 16
81*4882a593Smuzhiyun #define ARM_MAX_HBP_SLOTS (ARM_MAX_BRP + ARM_MAX_WRP)
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* DSCR method of entry bits. */
84*4882a593Smuzhiyun #define ARM_DSCR_MOE(x) ((x >> 2) & 0xf)
85*4882a593Smuzhiyun #define ARM_ENTRY_BREAKPOINT 0x1
86*4882a593Smuzhiyun #define ARM_ENTRY_ASYNC_WATCHPOINT 0x2
87*4882a593Smuzhiyun #define ARM_ENTRY_SYNC_WATCHPOINT 0xa
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* DSCR monitor/halting bits. */
90*4882a593Smuzhiyun #define ARM_DSCR_HDBGEN (1 << 14)
91*4882a593Smuzhiyun #define ARM_DSCR_MDBGEN (1 << 15)
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* OSLSR os lock model bits */
94*4882a593Smuzhiyun #define ARM_OSLSR_OSLM0 (1 << 0)
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* opcode2 numbers for the co-processor instructions. */
97*4882a593Smuzhiyun #define ARM_OP2_BVR 4
98*4882a593Smuzhiyun #define ARM_OP2_BCR 5
99*4882a593Smuzhiyun #define ARM_OP2_WVR 6
100*4882a593Smuzhiyun #define ARM_OP2_WCR 7
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* Base register numbers for the debug registers. */
103*4882a593Smuzhiyun #define ARM_BASE_BVR 64
104*4882a593Smuzhiyun #define ARM_BASE_BCR 80
105*4882a593Smuzhiyun #define ARM_BASE_WVR 96
106*4882a593Smuzhiyun #define ARM_BASE_WCR 112
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* Accessor macros for the debug registers. */
109*4882a593Smuzhiyun #define ARM_DBG_READ(N, M, OP2, VAL) do {\
110*4882a593Smuzhiyun asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
111*4882a593Smuzhiyun } while (0)
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\
114*4882a593Smuzhiyun asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
115*4882a593Smuzhiyun } while (0)
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun struct perf_event_attr;
118*4882a593Smuzhiyun struct notifier_block;
119*4882a593Smuzhiyun struct perf_event;
120*4882a593Smuzhiyun struct pmu;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
123*4882a593Smuzhiyun int *gen_len, int *gen_type);
124*4882a593Smuzhiyun extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw);
125*4882a593Smuzhiyun extern int hw_breakpoint_arch_parse(struct perf_event *bp,
126*4882a593Smuzhiyun const struct perf_event_attr *attr,
127*4882a593Smuzhiyun struct arch_hw_breakpoint *hw);
128*4882a593Smuzhiyun extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
129*4882a593Smuzhiyun unsigned long val, void *data);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun extern u8 arch_get_debug_arch(void);
132*4882a593Smuzhiyun extern u8 arch_get_max_wp_len(void);
133*4882a593Smuzhiyun extern void clear_ptrace_hw_breakpoint(struct task_struct *tsk);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun int arch_install_hw_breakpoint(struct perf_event *bp);
136*4882a593Smuzhiyun void arch_uninstall_hw_breakpoint(struct perf_event *bp);
137*4882a593Smuzhiyun void hw_breakpoint_pmu_read(struct perf_event *bp);
138*4882a593Smuzhiyun int hw_breakpoint_slots(int type);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun #else
clear_ptrace_hw_breakpoint(struct task_struct * tsk)141*4882a593Smuzhiyun static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {}
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun #endif /* CONFIG_HAVE_HW_BREAKPOINT */
144*4882a593Smuzhiyun #endif /* __KERNEL__ */
145*4882a593Smuzhiyun #endif /* _ARM_HW_BREAKPOINT_H */
146