xref: /OK3568_Linux_fs/kernel/arch/arm/include/asm/hardware/iomd.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  arch/arm/include/asm/hardware/iomd.h
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright (C) 1999 Russell King
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  *  This file contains information out the IOMD ASIC used in the
8*4882a593Smuzhiyun  *  Acorn RiscPC and subsequently integrated into the CLPS7500 chips.
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun #ifndef __ASMARM_HARDWARE_IOMD_H
11*4882a593Smuzhiyun #define __ASMARM_HARDWARE_IOMD_H
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #ifndef __ASSEMBLY__
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun  * We use __raw_base variants here so that we give the compiler the
18*4882a593Smuzhiyun  * chance to keep IOC_BASE in a register.
19*4882a593Smuzhiyun  */
20*4882a593Smuzhiyun #define iomd_readb(off)		__raw_readb(IOMD_BASE + (off))
21*4882a593Smuzhiyun #define iomd_readl(off)		__raw_readl(IOMD_BASE + (off))
22*4882a593Smuzhiyun #define iomd_writeb(val,off)	__raw_writeb(val, IOMD_BASE + (off))
23*4882a593Smuzhiyun #define iomd_writel(val,off)	__raw_writel(val, IOMD_BASE + (off))
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define IOMD_CONTROL	(0x000)
28*4882a593Smuzhiyun #define IOMD_KARTTX	(0x004)
29*4882a593Smuzhiyun #define IOMD_KARTRX	(0x004)
30*4882a593Smuzhiyun #define IOMD_KCTRL	(0x008)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define IOMD_IRQSTATA	(0x010)
33*4882a593Smuzhiyun #define IOMD_IRQREQA	(0x014)
34*4882a593Smuzhiyun #define IOMD_IRQCLRA	(0x014)
35*4882a593Smuzhiyun #define IOMD_IRQMASKA	(0x018)
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define IOMD_IRQSTATB	(0x020)
38*4882a593Smuzhiyun #define IOMD_IRQREQB	(0x024)
39*4882a593Smuzhiyun #define IOMD_IRQMASKB	(0x028)
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define IOMD_FIQSTAT	(0x030)
42*4882a593Smuzhiyun #define IOMD_FIQREQ	(0x034)
43*4882a593Smuzhiyun #define IOMD_FIQMASK	(0x038)
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define IOMD_T0CNTL	(0x040)
46*4882a593Smuzhiyun #define IOMD_T0LTCHL	(0x040)
47*4882a593Smuzhiyun #define IOMD_T0CNTH	(0x044)
48*4882a593Smuzhiyun #define IOMD_T0LTCHH	(0x044)
49*4882a593Smuzhiyun #define IOMD_T0GO	(0x048)
50*4882a593Smuzhiyun #define IOMD_T0LATCH	(0x04c)
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define IOMD_T1CNTL	(0x050)
53*4882a593Smuzhiyun #define IOMD_T1LTCHL	(0x050)
54*4882a593Smuzhiyun #define IOMD_T1CNTH	(0x054)
55*4882a593Smuzhiyun #define IOMD_T1LTCHH	(0x054)
56*4882a593Smuzhiyun #define IOMD_T1GO	(0x058)
57*4882a593Smuzhiyun #define IOMD_T1LATCH	(0x05c)
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define IOMD_ROMCR0	(0x080)
60*4882a593Smuzhiyun #define IOMD_ROMCR1	(0x084)
61*4882a593Smuzhiyun #ifdef CONFIG_ARCH_RPC
62*4882a593Smuzhiyun #define IOMD_DRAMCR	(0x088)
63*4882a593Smuzhiyun #endif
64*4882a593Smuzhiyun #define IOMD_REFCR	(0x08C)
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define IOMD_FSIZE	(0x090)
67*4882a593Smuzhiyun #define IOMD_ID0	(0x094)
68*4882a593Smuzhiyun #define IOMD_ID1	(0x098)
69*4882a593Smuzhiyun #define IOMD_VERSION	(0x09C)
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #ifdef CONFIG_ARCH_RPC
72*4882a593Smuzhiyun #define IOMD_MOUSEX	(0x0A0)
73*4882a593Smuzhiyun #define IOMD_MOUSEY	(0x0A4)
74*4882a593Smuzhiyun #endif
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun #ifdef CONFIG_ARCH_RPC
77*4882a593Smuzhiyun #define IOMD_DMATCR	(0x0C0)
78*4882a593Smuzhiyun #endif
79*4882a593Smuzhiyun #define IOMD_IOTCR	(0x0C4)
80*4882a593Smuzhiyun #define IOMD_ECTCR	(0x0C8)
81*4882a593Smuzhiyun #ifdef CONFIG_ARCH_RPC
82*4882a593Smuzhiyun #define IOMD_DMAEXT	(0x0CC)
83*4882a593Smuzhiyun #endif
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #ifdef CONFIG_ARCH_RPC
86*4882a593Smuzhiyun #define DMA_EXT_IO0	1
87*4882a593Smuzhiyun #define DMA_EXT_IO1	2
88*4882a593Smuzhiyun #define DMA_EXT_IO2	4
89*4882a593Smuzhiyun #define DMA_EXT_IO3	8
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun #define IOMD_IO0CURA	(0x100)
92*4882a593Smuzhiyun #define IOMD_IO0ENDA	(0x104)
93*4882a593Smuzhiyun #define IOMD_IO0CURB	(0x108)
94*4882a593Smuzhiyun #define IOMD_IO0ENDB	(0x10C)
95*4882a593Smuzhiyun #define IOMD_IO0CR	(0x110)
96*4882a593Smuzhiyun #define IOMD_IO0ST	(0x114)
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define IOMD_IO1CURA	(0x120)
99*4882a593Smuzhiyun #define IOMD_IO1ENDA	(0x124)
100*4882a593Smuzhiyun #define IOMD_IO1CURB	(0x128)
101*4882a593Smuzhiyun #define IOMD_IO1ENDB	(0x12C)
102*4882a593Smuzhiyun #define IOMD_IO1CR	(0x130)
103*4882a593Smuzhiyun #define IOMD_IO1ST	(0x134)
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun #define IOMD_IO2CURA	(0x140)
106*4882a593Smuzhiyun #define IOMD_IO2ENDA	(0x144)
107*4882a593Smuzhiyun #define IOMD_IO2CURB	(0x148)
108*4882a593Smuzhiyun #define IOMD_IO2ENDB	(0x14C)
109*4882a593Smuzhiyun #define IOMD_IO2CR	(0x150)
110*4882a593Smuzhiyun #define IOMD_IO2ST	(0x154)
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun #define IOMD_IO3CURA	(0x160)
113*4882a593Smuzhiyun #define IOMD_IO3ENDA	(0x164)
114*4882a593Smuzhiyun #define IOMD_IO3CURB	(0x168)
115*4882a593Smuzhiyun #define IOMD_IO3ENDB	(0x16C)
116*4882a593Smuzhiyun #define IOMD_IO3CR	(0x170)
117*4882a593Smuzhiyun #define IOMD_IO3ST	(0x174)
118*4882a593Smuzhiyun #endif
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun #define IOMD_SD0CURA	(0x180)
121*4882a593Smuzhiyun #define IOMD_SD0ENDA	(0x184)
122*4882a593Smuzhiyun #define IOMD_SD0CURB	(0x188)
123*4882a593Smuzhiyun #define IOMD_SD0ENDB	(0x18C)
124*4882a593Smuzhiyun #define IOMD_SD0CR	(0x190)
125*4882a593Smuzhiyun #define IOMD_SD0ST	(0x194)
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun #ifdef CONFIG_ARCH_RPC
128*4882a593Smuzhiyun #define IOMD_SD1CURA	(0x1A0)
129*4882a593Smuzhiyun #define IOMD_SD1ENDA	(0x1A4)
130*4882a593Smuzhiyun #define IOMD_SD1CURB	(0x1A8)
131*4882a593Smuzhiyun #define IOMD_SD1ENDB	(0x1AC)
132*4882a593Smuzhiyun #define IOMD_SD1CR	(0x1B0)
133*4882a593Smuzhiyun #define IOMD_SD1ST	(0x1B4)
134*4882a593Smuzhiyun #endif
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun #define IOMD_CURSCUR	(0x1C0)
137*4882a593Smuzhiyun #define IOMD_CURSINIT	(0x1C4)
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun #define IOMD_VIDCUR	(0x1D0)
140*4882a593Smuzhiyun #define IOMD_VIDEND	(0x1D4)
141*4882a593Smuzhiyun #define IOMD_VIDSTART	(0x1D8)
142*4882a593Smuzhiyun #define IOMD_VIDINIT	(0x1DC)
143*4882a593Smuzhiyun #define IOMD_VIDCR	(0x1E0)
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun #define IOMD_DMASTAT	(0x1F0)
146*4882a593Smuzhiyun #define IOMD_DMAREQ	(0x1F4)
147*4882a593Smuzhiyun #define IOMD_DMAMASK	(0x1F8)
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun #define DMA_END_S	(1 << 31)
150*4882a593Smuzhiyun #define DMA_END_L	(1 << 30)
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun #define DMA_CR_C	0x80
153*4882a593Smuzhiyun #define DMA_CR_D	0x40
154*4882a593Smuzhiyun #define DMA_CR_E	0x20
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun #define DMA_ST_OFL	4
157*4882a593Smuzhiyun #define DMA_ST_INT	2
158*4882a593Smuzhiyun #define DMA_ST_AB	1
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun /*
161*4882a593Smuzhiyun  * DMA (MEMC) compatibility
162*4882a593Smuzhiyun  */
163*4882a593Smuzhiyun #define HALF_SAM	vram_half_sam
164*4882a593Smuzhiyun #define VDMA_ALIGNMENT	(HALF_SAM * 2)
165*4882a593Smuzhiyun #define VDMA_XFERSIZE	(HALF_SAM)
166*4882a593Smuzhiyun #define VDMA_INIT	IOMD_VIDINIT
167*4882a593Smuzhiyun #define VDMA_START	IOMD_VIDSTART
168*4882a593Smuzhiyun #define VDMA_END	IOMD_VIDEND
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun #ifndef __ASSEMBLY__
171*4882a593Smuzhiyun extern unsigned int vram_half_sam;
172*4882a593Smuzhiyun #define video_set_dma(start,end,offset)				\
173*4882a593Smuzhiyun do {								\
174*4882a593Smuzhiyun 	outl (SCREEN_START + start, VDMA_START);		\
175*4882a593Smuzhiyun 	outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END);	\
176*4882a593Smuzhiyun 	if (offset >= end - VDMA_XFERSIZE)			\
177*4882a593Smuzhiyun 		offset |= 0x40000000;				\
178*4882a593Smuzhiyun 	outl (SCREEN_START + offset, VDMA_INIT);		\
179*4882a593Smuzhiyun } while (0)
180*4882a593Smuzhiyun #endif
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun #endif
183