1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/include/asm/hardware/ioc.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) Russell King 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Use these macros to read/write the IOC. All it does is perform the actual 8*4882a593Smuzhiyun * read/write. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef __ASMARM_HARDWARE_IOC_H 11*4882a593Smuzhiyun #define __ASMARM_HARDWARE_IOC_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * We use __raw_base variants here so that we give the compiler the 17*4882a593Smuzhiyun * chance to keep IOC_BASE in a register. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define ioc_readb(off) __raw_readb(IOC_BASE + (off)) 20*4882a593Smuzhiyun #define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off)) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #endif 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define IOC_CONTROL (0x00) 25*4882a593Smuzhiyun #define IOC_KARTTX (0x04) 26*4882a593Smuzhiyun #define IOC_KARTRX (0x04) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define IOC_IRQSTATA (0x10) 29*4882a593Smuzhiyun #define IOC_IRQREQA (0x14) 30*4882a593Smuzhiyun #define IOC_IRQCLRA (0x14) 31*4882a593Smuzhiyun #define IOC_IRQMASKA (0x18) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define IOC_IRQSTATB (0x20) 34*4882a593Smuzhiyun #define IOC_IRQREQB (0x24) 35*4882a593Smuzhiyun #define IOC_IRQMASKB (0x28) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define IOC_FIQSTAT (0x30) 38*4882a593Smuzhiyun #define IOC_FIQREQ (0x34) 39*4882a593Smuzhiyun #define IOC_FIQMASK (0x38) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define IOC_T0CNTL (0x40) 42*4882a593Smuzhiyun #define IOC_T0LTCHL (0x40) 43*4882a593Smuzhiyun #define IOC_T0CNTH (0x44) 44*4882a593Smuzhiyun #define IOC_T0LTCHH (0x44) 45*4882a593Smuzhiyun #define IOC_T0GO (0x48) 46*4882a593Smuzhiyun #define IOC_T0LATCH (0x4c) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define IOC_T1CNTL (0x50) 49*4882a593Smuzhiyun #define IOC_T1LTCHL (0x50) 50*4882a593Smuzhiyun #define IOC_T1CNTH (0x54) 51*4882a593Smuzhiyun #define IOC_T1LTCHH (0x54) 52*4882a593Smuzhiyun #define IOC_T1GO (0x58) 53*4882a593Smuzhiyun #define IOC_T1LATCH (0x5c) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define IOC_T2CNTL (0x60) 56*4882a593Smuzhiyun #define IOC_T2LTCHL (0x60) 57*4882a593Smuzhiyun #define IOC_T2CNTH (0x64) 58*4882a593Smuzhiyun #define IOC_T2LTCHH (0x64) 59*4882a593Smuzhiyun #define IOC_T2GO (0x68) 60*4882a593Smuzhiyun #define IOC_T2LATCH (0x6c) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define IOC_T3CNTL (0x70) 63*4882a593Smuzhiyun #define IOC_T3LTCHL (0x70) 64*4882a593Smuzhiyun #define IOC_T3CNTH (0x74) 65*4882a593Smuzhiyun #define IOC_T3LTCHH (0x74) 66*4882a593Smuzhiyun #define IOC_T3GO (0x78) 67*4882a593Smuzhiyun #define IOC_T3LATCH (0x7c) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif 70