1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * AURORA shared L2 cache controller support 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2012 Marvell 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Yehuda Yitschak <yehuday@marvell.com> 7*4882a593Smuzhiyun * Gregory CLEMENT <gregory.clement@free-electrons.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 10*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 11*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __ASM_ARM_HARDWARE_AURORA_L2_H 15*4882a593Smuzhiyun #define __ASM_ARM_HARDWARE_AURORA_L2_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define AURORA_SYNC_REG 0x700 18*4882a593Smuzhiyun #define AURORA_RANGE_BASE_ADDR_REG 0x720 19*4882a593Smuzhiyun #define AURORA_FLUSH_PHY_ADDR_REG 0x7f0 20*4882a593Smuzhiyun #define AURORA_INVAL_RANGE_REG 0x774 21*4882a593Smuzhiyun #define AURORA_CLEAN_RANGE_REG 0x7b4 22*4882a593Smuzhiyun #define AURORA_FLUSH_RANGE_REG 0x7f4 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define AURORA_ACR_REPLACEMENT_OFFSET 27 25*4882a593Smuzhiyun #define AURORA_ACR_REPLACEMENT_MASK \ 26*4882a593Smuzhiyun (0x3 << AURORA_ACR_REPLACEMENT_OFFSET) 27*4882a593Smuzhiyun #define AURORA_ACR_REPLACEMENT_TYPE_WAYRR \ 28*4882a593Smuzhiyun (0 << AURORA_ACR_REPLACEMENT_OFFSET) 29*4882a593Smuzhiyun #define AURORA_ACR_REPLACEMENT_TYPE_LFSR \ 30*4882a593Smuzhiyun (1 << AURORA_ACR_REPLACEMENT_OFFSET) 31*4882a593Smuzhiyun #define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \ 32*4882a593Smuzhiyun (3 << AURORA_ACR_REPLACEMENT_OFFSET) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define AURORA_ACR_PARITY_EN (1 << 21) 35*4882a593Smuzhiyun #define AURORA_ACR_ECC_EN (1 << 20) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0 38*4882a593Smuzhiyun #define AURORA_ACR_FORCE_WRITE_POLICY_MASK \ 39*4882a593Smuzhiyun (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 40*4882a593Smuzhiyun #define AURORA_ACR_FORCE_WRITE_POLICY_DIS \ 41*4882a593Smuzhiyun (0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 42*4882a593Smuzhiyun #define AURORA_ACR_FORCE_WRITE_BACK_POLICY \ 43*4882a593Smuzhiyun (1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 44*4882a593Smuzhiyun #define AURORA_ACR_FORCE_WRITE_THRO_POLICY \ 45*4882a593Smuzhiyun (2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define AURORA_ERR_CNT_REG 0x600 48*4882a593Smuzhiyun #define AURORA_ERR_ATTR_CAP_REG 0x608 49*4882a593Smuzhiyun #define AURORA_ERR_ADDR_CAP_REG 0x60c 50*4882a593Smuzhiyun #define AURORA_ERR_WAY_CAP_REG 0x610 51*4882a593Smuzhiyun #define AURORA_ERR_INJECT_CTL_REG 0x614 52*4882a593Smuzhiyun #define AURORA_ERR_INJECT_MASK_REG 0x618 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define AURORA_ERR_CNT_CLR_OFFSET 31 55*4882a593Smuzhiyun #define AURORA_ERR_CNT_CLR \ 56*4882a593Smuzhiyun (0x1 << AURORA_ERR_CNT_CLR_OFFSET) 57*4882a593Smuzhiyun #define AURORA_ERR_CNT_UE_OFFSET 16 58*4882a593Smuzhiyun #define AURORA_ERR_CNT_UE_MASK \ 59*4882a593Smuzhiyun (0x7fff << AURORA_ERR_CNT_UE_OFFSET) 60*4882a593Smuzhiyun #define AURORA_ERR_CNT_CE_OFFSET 0 61*4882a593Smuzhiyun #define AURORA_ERR_CNT_CE_MASK \ 62*4882a593Smuzhiyun (0xffff << AURORA_ERR_CNT_CE_OFFSET) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define AURORA_ERR_ATTR_SRC_OFF 16 65*4882a593Smuzhiyun #define AURORA_ERR_ATTR_SRC_MSK \ 66*4882a593Smuzhiyun (0x7 << AURORA_ERR_ATTR_SRC_OFF) 67*4882a593Smuzhiyun #define AURORA_ERR_ATTR_TXN_OFF 12 68*4882a593Smuzhiyun #define AURORA_ERR_ATTR_TXN_MSK \ 69*4882a593Smuzhiyun (0xf << AURORA_ERR_ATTR_TXN_OFF) 70*4882a593Smuzhiyun #define AURORA_ERR_ATTR_ERR_OFF 8 71*4882a593Smuzhiyun #define AURORA_ERR_ATTR_ERR_MSK \ 72*4882a593Smuzhiyun (0x3 << AURORA_ERR_ATTR_ERR_OFF) 73*4882a593Smuzhiyun #define AURORA_ERR_ATTR_CAP_VALID_OFF 0 74*4882a593Smuzhiyun #define AURORA_ERR_ATTR_CAP_VALID \ 75*4882a593Smuzhiyun (0x1 << AURORA_ERR_ATTR_CAP_VALID_OFF) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define AURORA_ERR_ADDR_CAP_ADDR_MASK 0xffffffe0 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define AURORA_ERR_WAY_IDX_OFF 8 80*4882a593Smuzhiyun #define AURORA_ERR_WAY_IDX_MSK \ 81*4882a593Smuzhiyun (0xfff << AURORA_ERR_WAY_IDX_OFF) 82*4882a593Smuzhiyun #define AURORA_ERR_WAY_CAP_WAY_OFFSET 1 83*4882a593Smuzhiyun #define AURORA_ERR_WAY_CAP_WAY_MASK \ 84*4882a593Smuzhiyun (0xf << AURORA_ERR_WAY_CAP_WAY_OFFSET) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define AURORA_ERR_INJECT_CTL_ADDR_MASK 0xfffffff0 87*4882a593Smuzhiyun #define AURORA_ERR_ATTR_TXN_OFF 12 88*4882a593Smuzhiyun #define AURORA_ERR_INJECT_CTL_EN_MASK 0x3 89*4882a593Smuzhiyun #define AURORA_ERR_INJECT_CTL_EN_PARITY 0x2 90*4882a593Smuzhiyun #define AURORA_ERR_INJECT_CTL_EN_ECC 0x1 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define AURORA_MAX_RANGE_SIZE 1024 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define AURORA_WAY_SIZE_SHIFT 2 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define AURORA_CTRL_FW 0x100 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make 99*4882a593Smuzhiyun * the distinction between a number coming from hardware and a number 100*4882a593Smuzhiyun * coming from the device tree */ 101*4882a593Smuzhiyun #define AURORA_CACHE_ID 0x100 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */ 104