1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/include/asm/glue-cache.h
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 1999-2002 Russell King
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #ifndef ASM_GLUE_CACHE_H
8*4882a593Smuzhiyun #define ASM_GLUE_CACHE_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <asm/glue.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /*
13*4882a593Smuzhiyun * Cache Model
14*4882a593Smuzhiyun * ===========
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun #undef _CACHE
17*4882a593Smuzhiyun #undef MULTI_CACHE
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #if defined(CONFIG_CPU_CACHE_V4)
20*4882a593Smuzhiyun # ifdef _CACHE
21*4882a593Smuzhiyun # define MULTI_CACHE 1
22*4882a593Smuzhiyun # else
23*4882a593Smuzhiyun # define _CACHE v4
24*4882a593Smuzhiyun # endif
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
28*4882a593Smuzhiyun defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \
29*4882a593Smuzhiyun defined(CONFIG_CPU_ARM1026)
30*4882a593Smuzhiyun # define MULTI_CACHE 1
31*4882a593Smuzhiyun #endif
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #if defined(CONFIG_CPU_FA526)
34*4882a593Smuzhiyun # ifdef _CACHE
35*4882a593Smuzhiyun # define MULTI_CACHE 1
36*4882a593Smuzhiyun # else
37*4882a593Smuzhiyun # define _CACHE fa
38*4882a593Smuzhiyun # endif
39*4882a593Smuzhiyun #endif
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #if defined(CONFIG_CPU_ARM926T)
42*4882a593Smuzhiyun # ifdef _CACHE
43*4882a593Smuzhiyun # define MULTI_CACHE 1
44*4882a593Smuzhiyun # else
45*4882a593Smuzhiyun # define _CACHE arm926
46*4882a593Smuzhiyun # endif
47*4882a593Smuzhiyun #endif
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #if defined(CONFIG_CPU_ARM940T)
50*4882a593Smuzhiyun # ifdef _CACHE
51*4882a593Smuzhiyun # define MULTI_CACHE 1
52*4882a593Smuzhiyun # else
53*4882a593Smuzhiyun # define _CACHE arm940
54*4882a593Smuzhiyun # endif
55*4882a593Smuzhiyun #endif
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #if defined(CONFIG_CPU_ARM946E)
58*4882a593Smuzhiyun # ifdef _CACHE
59*4882a593Smuzhiyun # define MULTI_CACHE 1
60*4882a593Smuzhiyun # else
61*4882a593Smuzhiyun # define _CACHE arm946
62*4882a593Smuzhiyun # endif
63*4882a593Smuzhiyun #endif
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #if defined(CONFIG_CPU_CACHE_V4WB)
66*4882a593Smuzhiyun # ifdef _CACHE
67*4882a593Smuzhiyun # define MULTI_CACHE 1
68*4882a593Smuzhiyun # else
69*4882a593Smuzhiyun # define _CACHE v4wb
70*4882a593Smuzhiyun # endif
71*4882a593Smuzhiyun #endif
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #if defined(CONFIG_CPU_XSCALE)
74*4882a593Smuzhiyun # ifdef _CACHE
75*4882a593Smuzhiyun # define MULTI_CACHE 1
76*4882a593Smuzhiyun # else
77*4882a593Smuzhiyun # define _CACHE xscale
78*4882a593Smuzhiyun # endif
79*4882a593Smuzhiyun #endif
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #if defined(CONFIG_CPU_XSC3)
82*4882a593Smuzhiyun # ifdef _CACHE
83*4882a593Smuzhiyun # define MULTI_CACHE 1
84*4882a593Smuzhiyun # else
85*4882a593Smuzhiyun # define _CACHE xsc3
86*4882a593Smuzhiyun # endif
87*4882a593Smuzhiyun #endif
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun #if defined(CONFIG_CPU_MOHAWK)
90*4882a593Smuzhiyun # ifdef _CACHE
91*4882a593Smuzhiyun # define MULTI_CACHE 1
92*4882a593Smuzhiyun # else
93*4882a593Smuzhiyun # define _CACHE mohawk
94*4882a593Smuzhiyun # endif
95*4882a593Smuzhiyun #endif
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #if defined(CONFIG_CPU_FEROCEON)
98*4882a593Smuzhiyun # define MULTI_CACHE 1
99*4882a593Smuzhiyun #endif
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
102*4882a593Smuzhiyun # ifdef _CACHE
103*4882a593Smuzhiyun # define MULTI_CACHE 1
104*4882a593Smuzhiyun # else
105*4882a593Smuzhiyun # define _CACHE v6
106*4882a593Smuzhiyun # endif
107*4882a593Smuzhiyun #endif
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun #if defined(CONFIG_CPU_V7)
110*4882a593Smuzhiyun # ifdef _CACHE
111*4882a593Smuzhiyun # define MULTI_CACHE 1
112*4882a593Smuzhiyun # else
113*4882a593Smuzhiyun # define _CACHE v7
114*4882a593Smuzhiyun # endif
115*4882a593Smuzhiyun #endif
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun #if defined(CONFIG_CACHE_B15_RAC)
118*4882a593Smuzhiyun # define MULTI_CACHE 1
119*4882a593Smuzhiyun #endif
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #if defined(CONFIG_CPU_V7M)
122*4882a593Smuzhiyun # define MULTI_CACHE 1
123*4882a593Smuzhiyun #endif
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun #if !defined(_CACHE) && !defined(MULTI_CACHE)
126*4882a593Smuzhiyun #error Unknown cache maintenance model
127*4882a593Smuzhiyun #endif
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun #ifndef __ASSEMBLER__
nop_flush_icache_all(void)130*4882a593Smuzhiyun static inline void nop_flush_icache_all(void) { }
nop_flush_kern_cache_all(void)131*4882a593Smuzhiyun static inline void nop_flush_kern_cache_all(void) { }
nop_flush_kern_cache_louis(void)132*4882a593Smuzhiyun static inline void nop_flush_kern_cache_louis(void) { }
nop_flush_user_cache_all(void)133*4882a593Smuzhiyun static inline void nop_flush_user_cache_all(void) { }
nop_flush_user_cache_range(unsigned long a,unsigned long b,unsigned int c)134*4882a593Smuzhiyun static inline void nop_flush_user_cache_range(unsigned long a,
135*4882a593Smuzhiyun unsigned long b, unsigned int c) { }
136*4882a593Smuzhiyun
nop_coherent_kern_range(unsigned long a,unsigned long b)137*4882a593Smuzhiyun static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
nop_coherent_user_range(unsigned long a,unsigned long b)138*4882a593Smuzhiyun static inline int nop_coherent_user_range(unsigned long a,
139*4882a593Smuzhiyun unsigned long b) { return 0; }
nop_flush_kern_dcache_area(void * a,size_t s)140*4882a593Smuzhiyun static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
141*4882a593Smuzhiyun
nop_dma_flush_range(const void * a,const void * b)142*4882a593Smuzhiyun static inline void nop_dma_flush_range(const void *a, const void *b) { }
143*4882a593Smuzhiyun
nop_dma_map_area(const void * s,size_t l,int f)144*4882a593Smuzhiyun static inline void nop_dma_map_area(const void *s, size_t l, int f) { }
nop_dma_unmap_area(const void * s,size_t l,int f)145*4882a593Smuzhiyun static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
146*4882a593Smuzhiyun #endif
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun #ifndef MULTI_CACHE
149*4882a593Smuzhiyun #define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all)
150*4882a593Smuzhiyun #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
151*4882a593Smuzhiyun #define __cpuc_flush_kern_louis __glue(_CACHE,_flush_kern_cache_louis)
152*4882a593Smuzhiyun #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
153*4882a593Smuzhiyun #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
154*4882a593Smuzhiyun #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
155*4882a593Smuzhiyun #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
156*4882a593Smuzhiyun #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun #define dmac_flush_range __glue(_CACHE,_dma_flush_range)
159*4882a593Smuzhiyun #endif
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun #endif
162