1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef __ASM_BARRIER_H
3*4882a593Smuzhiyun #define __ASM_BARRIER_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #ifndef __ASSEMBLY__
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #if __LINUX_ARM_ARCH__ >= 7 || \
10*4882a593Smuzhiyun (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
11*4882a593Smuzhiyun #define sev() __asm__ __volatile__ ("sev" : : : "memory")
12*4882a593Smuzhiyun #define wfe() __asm__ __volatile__ ("wfe" : : : "memory")
13*4882a593Smuzhiyun #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
14*4882a593Smuzhiyun #else
15*4882a593Smuzhiyun #define wfe() do { } while (0)
16*4882a593Smuzhiyun #endif
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #if __LINUX_ARM_ARCH__ >= 7
19*4882a593Smuzhiyun #define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory")
20*4882a593Smuzhiyun #define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory")
21*4882a593Smuzhiyun #define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")
22*4882a593Smuzhiyun #ifdef CONFIG_THUMB2_KERNEL
23*4882a593Smuzhiyun #define CSDB ".inst.w 0xf3af8014"
24*4882a593Smuzhiyun #else
25*4882a593Smuzhiyun #define CSDB ".inst 0xe320f014"
26*4882a593Smuzhiyun #endif
27*4882a593Smuzhiyun #define csdb() __asm__ __volatile__(CSDB : : : "memory")
28*4882a593Smuzhiyun #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
29*4882a593Smuzhiyun #define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
30*4882a593Smuzhiyun : : "r" (0) : "memory")
31*4882a593Smuzhiyun #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
32*4882a593Smuzhiyun : : "r" (0) : "memory")
33*4882a593Smuzhiyun #define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
34*4882a593Smuzhiyun : : "r" (0) : "memory")
35*4882a593Smuzhiyun #elif defined(CONFIG_CPU_FA526)
36*4882a593Smuzhiyun #define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
37*4882a593Smuzhiyun : : "r" (0) : "memory")
38*4882a593Smuzhiyun #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
39*4882a593Smuzhiyun : : "r" (0) : "memory")
40*4882a593Smuzhiyun #define dmb(x) __asm__ __volatile__ ("" : : : "memory")
41*4882a593Smuzhiyun #else
42*4882a593Smuzhiyun #define isb(x) __asm__ __volatile__ ("" : : : "memory")
43*4882a593Smuzhiyun #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
44*4882a593Smuzhiyun : : "r" (0) : "memory")
45*4882a593Smuzhiyun #define dmb(x) __asm__ __volatile__ ("" : : : "memory")
46*4882a593Smuzhiyun #endif
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #ifndef CSDB
49*4882a593Smuzhiyun #define CSDB
50*4882a593Smuzhiyun #endif
51*4882a593Smuzhiyun #ifndef csdb
52*4882a593Smuzhiyun #define csdb()
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #ifdef CONFIG_ARM_HEAVY_MB
56*4882a593Smuzhiyun extern void (*soc_mb)(void);
57*4882a593Smuzhiyun extern void arm_heavy_mb(void);
58*4882a593Smuzhiyun #define __arm_heavy_mb(x...) do { dsb(x); arm_heavy_mb(); } while (0)
59*4882a593Smuzhiyun #else
60*4882a593Smuzhiyun #define __arm_heavy_mb(x...) dsb(x)
61*4882a593Smuzhiyun #endif
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #if defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
64*4882a593Smuzhiyun #define mb() __arm_heavy_mb()
65*4882a593Smuzhiyun #define rmb() dsb()
66*4882a593Smuzhiyun #define wmb() __arm_heavy_mb(st)
67*4882a593Smuzhiyun #define dma_rmb() dmb(osh)
68*4882a593Smuzhiyun #define dma_wmb() dmb(oshst)
69*4882a593Smuzhiyun #else
70*4882a593Smuzhiyun #define mb() barrier()
71*4882a593Smuzhiyun #define rmb() barrier()
72*4882a593Smuzhiyun #define wmb() barrier()
73*4882a593Smuzhiyun #define dma_rmb() barrier()
74*4882a593Smuzhiyun #define dma_wmb() barrier()
75*4882a593Smuzhiyun #endif
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #define __smp_mb() dmb(ish)
78*4882a593Smuzhiyun #define __smp_rmb() __smp_mb()
79*4882a593Smuzhiyun #define __smp_wmb() dmb(ishst)
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #ifdef CONFIG_CPU_SPECTRE
array_index_mask_nospec(unsigned long idx,unsigned long sz)82*4882a593Smuzhiyun static inline unsigned long array_index_mask_nospec(unsigned long idx,
83*4882a593Smuzhiyun unsigned long sz)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun unsigned long mask;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun asm volatile(
88*4882a593Smuzhiyun "cmp %1, %2\n"
89*4882a593Smuzhiyun " sbc %0, %1, %1\n"
90*4882a593Smuzhiyun CSDB
91*4882a593Smuzhiyun : "=r" (mask)
92*4882a593Smuzhiyun : "r" (idx), "Ir" (sz)
93*4882a593Smuzhiyun : "cc");
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return mask;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun #define array_index_mask_nospec array_index_mask_nospec
98*4882a593Smuzhiyun #endif
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun #include <asm-generic/barrier.h>
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */
103*4882a593Smuzhiyun #endif /* __ASM_BARRIER_H */
104