1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * sha1-ce-core.S - SHA-1 secure hash using ARMv8 Crypto Extensions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Linaro Ltd. 6*4882a593Smuzhiyun * Author: Ard Biesheuvel <ard.biesheuvel@linaro.org> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <linux/linkage.h> 10*4882a593Smuzhiyun#include <asm/assembler.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun .text 13*4882a593Smuzhiyun .arch armv8-a 14*4882a593Smuzhiyun .fpu crypto-neon-fp-armv8 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun k0 .req q0 17*4882a593Smuzhiyun k1 .req q1 18*4882a593Smuzhiyun k2 .req q2 19*4882a593Smuzhiyun k3 .req q3 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun ta0 .req q4 22*4882a593Smuzhiyun ta1 .req q5 23*4882a593Smuzhiyun tb0 .req q5 24*4882a593Smuzhiyun tb1 .req q4 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun dga .req q6 27*4882a593Smuzhiyun dgb .req q7 28*4882a593Smuzhiyun dgbs .req s28 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun dg0 .req q12 31*4882a593Smuzhiyun dg1a0 .req q13 32*4882a593Smuzhiyun dg1a1 .req q14 33*4882a593Smuzhiyun dg1b0 .req q14 34*4882a593Smuzhiyun dg1b1 .req q13 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun .macro add_only, op, ev, rc, s0, dg1 37*4882a593Smuzhiyun .ifnb \s0 38*4882a593Smuzhiyun vadd.u32 tb\ev, q\s0, \rc 39*4882a593Smuzhiyun .endif 40*4882a593Smuzhiyun sha1h.32 dg1b\ev, dg0 41*4882a593Smuzhiyun .ifb \dg1 42*4882a593Smuzhiyun sha1\op\().32 dg0, dg1a\ev, ta\ev 43*4882a593Smuzhiyun .else 44*4882a593Smuzhiyun sha1\op\().32 dg0, \dg1, ta\ev 45*4882a593Smuzhiyun .endif 46*4882a593Smuzhiyun .endm 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1 49*4882a593Smuzhiyun sha1su0.32 q\s0, q\s1, q\s2 50*4882a593Smuzhiyun add_only \op, \ev, \rc, \s1, \dg1 51*4882a593Smuzhiyun sha1su1.32 q\s0, q\s3 52*4882a593Smuzhiyun .endm 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun .align 6 55*4882a593Smuzhiyun.Lsha1_rcon: 56*4882a593Smuzhiyun .word 0x5a827999, 0x5a827999, 0x5a827999, 0x5a827999 57*4882a593Smuzhiyun .word 0x6ed9eba1, 0x6ed9eba1, 0x6ed9eba1, 0x6ed9eba1 58*4882a593Smuzhiyun .word 0x8f1bbcdc, 0x8f1bbcdc, 0x8f1bbcdc, 0x8f1bbcdc 59*4882a593Smuzhiyun .word 0xca62c1d6, 0xca62c1d6, 0xca62c1d6, 0xca62c1d6 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * void sha1_ce_transform(struct sha1_state *sst, u8 const *src, 63*4882a593Smuzhiyun * int blocks); 64*4882a593Smuzhiyun */ 65*4882a593SmuzhiyunENTRY(sha1_ce_transform) 66*4882a593Smuzhiyun /* load round constants */ 67*4882a593Smuzhiyun adr ip, .Lsha1_rcon 68*4882a593Smuzhiyun vld1.32 {k0-k1}, [ip, :128]! 69*4882a593Smuzhiyun vld1.32 {k2-k3}, [ip, :128] 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* load state */ 72*4882a593Smuzhiyun vld1.32 {dga}, [r0] 73*4882a593Smuzhiyun vldr dgbs, [r0, #16] 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* load input */ 76*4882a593Smuzhiyun0: vld1.32 {q8-q9}, [r1]! 77*4882a593Smuzhiyun vld1.32 {q10-q11}, [r1]! 78*4882a593Smuzhiyun subs r2, r2, #1 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun#ifndef CONFIG_CPU_BIG_ENDIAN 81*4882a593Smuzhiyun vrev32.8 q8, q8 82*4882a593Smuzhiyun vrev32.8 q9, q9 83*4882a593Smuzhiyun vrev32.8 q10, q10 84*4882a593Smuzhiyun vrev32.8 q11, q11 85*4882a593Smuzhiyun#endif 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun vadd.u32 ta0, q8, k0 88*4882a593Smuzhiyun vmov dg0, dga 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun add_update c, 0, k0, 8, 9, 10, 11, dgb 91*4882a593Smuzhiyun add_update c, 1, k0, 9, 10, 11, 8 92*4882a593Smuzhiyun add_update c, 0, k0, 10, 11, 8, 9 93*4882a593Smuzhiyun add_update c, 1, k0, 11, 8, 9, 10 94*4882a593Smuzhiyun add_update c, 0, k1, 8, 9, 10, 11 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun add_update p, 1, k1, 9, 10, 11, 8 97*4882a593Smuzhiyun add_update p, 0, k1, 10, 11, 8, 9 98*4882a593Smuzhiyun add_update p, 1, k1, 11, 8, 9, 10 99*4882a593Smuzhiyun add_update p, 0, k1, 8, 9, 10, 11 100*4882a593Smuzhiyun add_update p, 1, k2, 9, 10, 11, 8 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun add_update m, 0, k2, 10, 11, 8, 9 103*4882a593Smuzhiyun add_update m, 1, k2, 11, 8, 9, 10 104*4882a593Smuzhiyun add_update m, 0, k2, 8, 9, 10, 11 105*4882a593Smuzhiyun add_update m, 1, k2, 9, 10, 11, 8 106*4882a593Smuzhiyun add_update m, 0, k3, 10, 11, 8, 9 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun add_update p, 1, k3, 11, 8, 9, 10 109*4882a593Smuzhiyun add_only p, 0, k3, 9 110*4882a593Smuzhiyun add_only p, 1, k3, 10 111*4882a593Smuzhiyun add_only p, 0, k3, 11 112*4882a593Smuzhiyun add_only p, 1 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* update state */ 115*4882a593Smuzhiyun vadd.u32 dga, dga, dg0 116*4882a593Smuzhiyun vadd.u32 dgb, dgb, dg1a0 117*4882a593Smuzhiyun bne 0b 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* store new state */ 120*4882a593Smuzhiyun vst1.32 {dga}, [r0] 121*4882a593Smuzhiyun vstr dgbs, [r0, #16] 122*4882a593Smuzhiyun bx lr 123*4882a593SmuzhiyunENDPROC(sha1_ce_transform) 124