1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2014 Renesas Electronics Corporation 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Initialization of CNTVOFF register from secure mode 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <linux/linkage.h> 10*4882a593Smuzhiyun#include <asm/assembler.h> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunENTRY(secure_cntvoff_init) 13*4882a593Smuzhiyun .arch armv7-a 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * CNTVOFF has to be initialized either from non-secure Hypervisor 16*4882a593Smuzhiyun * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled 17*4882a593Smuzhiyun * then it should be handled by the secure code. The CPU must implement 18*4882a593Smuzhiyun * the virtualization extensions. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun cps #MON_MODE 21*4882a593Smuzhiyun mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */ 22*4882a593Smuzhiyun orr r0, r1, #1 23*4882a593Smuzhiyun mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */ 24*4882a593Smuzhiyun isb 25*4882a593Smuzhiyun mov r0, #0 26*4882a593Smuzhiyun mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */ 27*4882a593Smuzhiyun isb 28*4882a593Smuzhiyun mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */ 29*4882a593Smuzhiyun isb 30*4882a593Smuzhiyun cps #SVC_MODE 31*4882a593Smuzhiyun ret lr 32*4882a593SmuzhiyunENDPROC(secure_cntvoff_init) 33