xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/zynq-zc706.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun *  Copyright (C) 2011 - 2014 Xilinx
4*4882a593Smuzhiyun *  Copyright (C) 2012 National Instruments Corp.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include "zynq-7000.dtsi"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	model = "Xilinx ZC706 board";
11*4882a593Smuzhiyun	compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	aliases {
14*4882a593Smuzhiyun		ethernet0 = &gem0;
15*4882a593Smuzhiyun		i2c0 = &i2c0;
16*4882a593Smuzhiyun		serial0 = &uart1;
17*4882a593Smuzhiyun		mmc0 = &sdhci0;
18*4882a593Smuzhiyun	};
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	memory@0 {
21*4882a593Smuzhiyun		device_type = "memory";
22*4882a593Smuzhiyun		reg = <0x0 0x40000000>;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	chosen {
26*4882a593Smuzhiyun		bootargs = "";
27*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	usb_phy0: phy0 {
31*4882a593Smuzhiyun		compatible = "usb-nop-xceiv";
32*4882a593Smuzhiyun		#phy-cells = <0>;
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun&clkc {
37*4882a593Smuzhiyun	ps-clk-frequency = <33333333>;
38*4882a593Smuzhiyun};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun&gem0 {
41*4882a593Smuzhiyun	status = "okay";
42*4882a593Smuzhiyun	phy-mode = "rgmii-id";
43*4882a593Smuzhiyun	phy-handle = <&ethernet_phy>;
44*4882a593Smuzhiyun	pinctrl-names = "default";
45*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_gem0_default>;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	ethernet_phy: ethernet-phy@7 {
48*4882a593Smuzhiyun		reg = <7>;
49*4882a593Smuzhiyun		device_type = "ethernet-phy";
50*4882a593Smuzhiyun	};
51*4882a593Smuzhiyun};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun&gpio0 {
54*4882a593Smuzhiyun	pinctrl-names = "default";
55*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_gpio0_default>;
56*4882a593Smuzhiyun};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun&i2c0 {
59*4882a593Smuzhiyun	status = "okay";
60*4882a593Smuzhiyun	clock-frequency = <400000>;
61*4882a593Smuzhiyun	pinctrl-names = "default";
62*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c0_default>;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun	i2c-mux@74 {
65*4882a593Smuzhiyun		compatible = "nxp,pca9548";
66*4882a593Smuzhiyun		#address-cells = <1>;
67*4882a593Smuzhiyun		#size-cells = <0>;
68*4882a593Smuzhiyun		reg = <0x74>;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun		i2c@0 {
71*4882a593Smuzhiyun			#address-cells = <1>;
72*4882a593Smuzhiyun			#size-cells = <0>;
73*4882a593Smuzhiyun			reg = <0>;
74*4882a593Smuzhiyun			si570: clock-generator@5d {
75*4882a593Smuzhiyun				#clock-cells = <0>;
76*4882a593Smuzhiyun				compatible = "silabs,si570";
77*4882a593Smuzhiyun				temperature-stability = <50>;
78*4882a593Smuzhiyun				reg = <0x5d>;
79*4882a593Smuzhiyun				factory-fout = <156250000>;
80*4882a593Smuzhiyun				clock-frequency = <148500000>;
81*4882a593Smuzhiyun			};
82*4882a593Smuzhiyun		};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun		i2c@1 {
85*4882a593Smuzhiyun			#address-cells = <1>;
86*4882a593Smuzhiyun			#size-cells = <0>;
87*4882a593Smuzhiyun			reg = <1>;
88*4882a593Smuzhiyun			adv7511: hdmi-tx@39 {
89*4882a593Smuzhiyun				compatible = "adi,adv7511";
90*4882a593Smuzhiyun				reg = <0x39>;
91*4882a593Smuzhiyun				adi,input-depth = <8>;
92*4882a593Smuzhiyun				adi,input-colorspace = "yuv422";
93*4882a593Smuzhiyun				adi,input-clock = "1x";
94*4882a593Smuzhiyun				adi,input-style = <3>;
95*4882a593Smuzhiyun				adi,input-justification = "evenly";
96*4882a593Smuzhiyun			};
97*4882a593Smuzhiyun		};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun		i2c@2 {
100*4882a593Smuzhiyun			#address-cells = <1>;
101*4882a593Smuzhiyun			#size-cells = <0>;
102*4882a593Smuzhiyun			reg = <2>;
103*4882a593Smuzhiyun			eeprom@54 {
104*4882a593Smuzhiyun				compatible = "atmel,24c08";
105*4882a593Smuzhiyun				reg = <0x54>;
106*4882a593Smuzhiyun			};
107*4882a593Smuzhiyun		};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun		i2c@3 {
110*4882a593Smuzhiyun			#address-cells = <1>;
111*4882a593Smuzhiyun			#size-cells = <0>;
112*4882a593Smuzhiyun			reg = <3>;
113*4882a593Smuzhiyun			gpio@21 {
114*4882a593Smuzhiyun				compatible = "ti,tca6416";
115*4882a593Smuzhiyun				reg = <0x21>;
116*4882a593Smuzhiyun				gpio-controller;
117*4882a593Smuzhiyun				#gpio-cells = <2>;
118*4882a593Smuzhiyun			};
119*4882a593Smuzhiyun		};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun		i2c@4 {
122*4882a593Smuzhiyun			#address-cells = <1>;
123*4882a593Smuzhiyun			#size-cells = <0>;
124*4882a593Smuzhiyun			reg = <4>;
125*4882a593Smuzhiyun			rtc@51 {
126*4882a593Smuzhiyun				compatible = "nxp,pcf8563";
127*4882a593Smuzhiyun				reg = <0x51>;
128*4882a593Smuzhiyun			};
129*4882a593Smuzhiyun		};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun		i2c@7 {
132*4882a593Smuzhiyun			#address-cells = <1>;
133*4882a593Smuzhiyun			#size-cells = <0>;
134*4882a593Smuzhiyun			reg = <7>;
135*4882a593Smuzhiyun			ucd90120@65 {
136*4882a593Smuzhiyun				compatible = "ti,ucd90120";
137*4882a593Smuzhiyun				reg = <0x65>;
138*4882a593Smuzhiyun			};
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun&pinctrl0 {
144*4882a593Smuzhiyun	pinctrl_gem0_default: gem0-default {
145*4882a593Smuzhiyun		mux {
146*4882a593Smuzhiyun			function = "ethernet0";
147*4882a593Smuzhiyun			groups = "ethernet0_0_grp";
148*4882a593Smuzhiyun		};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun		conf {
151*4882a593Smuzhiyun			groups = "ethernet0_0_grp";
152*4882a593Smuzhiyun			slew-rate = <0>;
153*4882a593Smuzhiyun			io-standard = <4>;
154*4882a593Smuzhiyun		};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun		conf-rx {
157*4882a593Smuzhiyun			pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
158*4882a593Smuzhiyun			bias-high-impedance;
159*4882a593Smuzhiyun			low-power-disable;
160*4882a593Smuzhiyun		};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun		conf-tx {
163*4882a593Smuzhiyun			pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
164*4882a593Smuzhiyun			low-power-enable;
165*4882a593Smuzhiyun			bias-disable;
166*4882a593Smuzhiyun		};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun		mux-mdio {
169*4882a593Smuzhiyun			function = "mdio0";
170*4882a593Smuzhiyun			groups = "mdio0_0_grp";
171*4882a593Smuzhiyun		};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun		conf-mdio {
174*4882a593Smuzhiyun			groups = "mdio0_0_grp";
175*4882a593Smuzhiyun			slew-rate = <0>;
176*4882a593Smuzhiyun			io-standard = <1>;
177*4882a593Smuzhiyun			bias-disable;
178*4882a593Smuzhiyun		};
179*4882a593Smuzhiyun	};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun	pinctrl_gpio0_default: gpio0-default {
182*4882a593Smuzhiyun		mux {
183*4882a593Smuzhiyun			function = "gpio0";
184*4882a593Smuzhiyun			groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
185*4882a593Smuzhiyun		};
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun		conf {
188*4882a593Smuzhiyun			groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
189*4882a593Smuzhiyun			slew-rate = <0>;
190*4882a593Smuzhiyun			io-standard = <1>;
191*4882a593Smuzhiyun		};
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun		conf-pull-up {
194*4882a593Smuzhiyun			pins = "MIO46", "MIO47";
195*4882a593Smuzhiyun			bias-pull-up;
196*4882a593Smuzhiyun		};
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun		conf-pull-none {
199*4882a593Smuzhiyun			pins = "MIO7";
200*4882a593Smuzhiyun			bias-disable;
201*4882a593Smuzhiyun		};
202*4882a593Smuzhiyun	};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun	pinctrl_i2c0_default: i2c0-default {
205*4882a593Smuzhiyun		mux {
206*4882a593Smuzhiyun			groups = "i2c0_10_grp";
207*4882a593Smuzhiyun			function = "i2c0";
208*4882a593Smuzhiyun		};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun		conf {
211*4882a593Smuzhiyun			groups = "i2c0_10_grp";
212*4882a593Smuzhiyun			bias-pull-up;
213*4882a593Smuzhiyun			slew-rate = <0>;
214*4882a593Smuzhiyun			io-standard = <1>;
215*4882a593Smuzhiyun		};
216*4882a593Smuzhiyun	};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun	pinctrl_sdhci0_default: sdhci0-default {
219*4882a593Smuzhiyun		mux {
220*4882a593Smuzhiyun			groups = "sdio0_2_grp";
221*4882a593Smuzhiyun			function = "sdio0";
222*4882a593Smuzhiyun		};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun		conf {
225*4882a593Smuzhiyun			groups = "sdio0_2_grp";
226*4882a593Smuzhiyun			slew-rate = <0>;
227*4882a593Smuzhiyun			io-standard = <1>;
228*4882a593Smuzhiyun			bias-disable;
229*4882a593Smuzhiyun		};
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun		mux-cd {
232*4882a593Smuzhiyun			groups = "gpio0_14_grp";
233*4882a593Smuzhiyun			function = "sdio0_cd";
234*4882a593Smuzhiyun		};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun		conf-cd {
237*4882a593Smuzhiyun			groups = "gpio0_14_grp";
238*4882a593Smuzhiyun			bias-high-impedance;
239*4882a593Smuzhiyun			bias-pull-up;
240*4882a593Smuzhiyun			slew-rate = <0>;
241*4882a593Smuzhiyun			io-standard = <1>;
242*4882a593Smuzhiyun		};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun		mux-wp {
245*4882a593Smuzhiyun			groups = "gpio0_15_grp";
246*4882a593Smuzhiyun			function = "sdio0_wp";
247*4882a593Smuzhiyun		};
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun		conf-wp {
250*4882a593Smuzhiyun			groups = "gpio0_15_grp";
251*4882a593Smuzhiyun			bias-high-impedance;
252*4882a593Smuzhiyun			bias-pull-up;
253*4882a593Smuzhiyun			slew-rate = <0>;
254*4882a593Smuzhiyun			io-standard = <1>;
255*4882a593Smuzhiyun		};
256*4882a593Smuzhiyun	};
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun	pinctrl_uart1_default: uart1-default {
259*4882a593Smuzhiyun		mux {
260*4882a593Smuzhiyun			groups = "uart1_10_grp";
261*4882a593Smuzhiyun			function = "uart1";
262*4882a593Smuzhiyun		};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun		conf {
265*4882a593Smuzhiyun			groups = "uart1_10_grp";
266*4882a593Smuzhiyun			slew-rate = <0>;
267*4882a593Smuzhiyun			io-standard = <1>;
268*4882a593Smuzhiyun		};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun		conf-rx {
271*4882a593Smuzhiyun			pins = "MIO49";
272*4882a593Smuzhiyun			bias-high-impedance;
273*4882a593Smuzhiyun		};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun		conf-tx {
276*4882a593Smuzhiyun			pins = "MIO48";
277*4882a593Smuzhiyun			bias-disable;
278*4882a593Smuzhiyun		};
279*4882a593Smuzhiyun	};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun	pinctrl_usb0_default: usb0-default {
282*4882a593Smuzhiyun		mux {
283*4882a593Smuzhiyun			groups = "usb0_0_grp";
284*4882a593Smuzhiyun			function = "usb0";
285*4882a593Smuzhiyun		};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun		conf {
288*4882a593Smuzhiyun			groups = "usb0_0_grp";
289*4882a593Smuzhiyun			slew-rate = <0>;
290*4882a593Smuzhiyun			io-standard = <1>;
291*4882a593Smuzhiyun		};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun		conf-rx {
294*4882a593Smuzhiyun			pins = "MIO29", "MIO31", "MIO36";
295*4882a593Smuzhiyun			bias-high-impedance;
296*4882a593Smuzhiyun		};
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun		conf-tx {
299*4882a593Smuzhiyun			pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
300*4882a593Smuzhiyun			       "MIO35", "MIO37", "MIO38", "MIO39";
301*4882a593Smuzhiyun			bias-disable;
302*4882a593Smuzhiyun		};
303*4882a593Smuzhiyun	};
304*4882a593Smuzhiyun};
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun&sdhci0 {
307*4882a593Smuzhiyun	status = "okay";
308*4882a593Smuzhiyun	pinctrl-names = "default";
309*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_sdhci0_default>;
310*4882a593Smuzhiyun};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun&uart1 {
313*4882a593Smuzhiyun	status = "okay";
314*4882a593Smuzhiyun	pinctrl-names = "default";
315*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1_default>;
316*4882a593Smuzhiyun};
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun&usb0 {
319*4882a593Smuzhiyun	status = "okay";
320*4882a593Smuzhiyun	dr_mode = "host";
321*4882a593Smuzhiyun	usb-phy = <&usb_phy0>;
322*4882a593Smuzhiyun	pinctrl-names = "default";
323*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usb0_default>;
324*4882a593Smuzhiyun};
325