1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * vt8500.dtsi - Device tree file for VIA VT8500 SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun #address-cells = <1>; 10*4882a593Smuzhiyun #size-cells = <1>; 11*4882a593Smuzhiyun compatible = "via,vt8500"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun cpus { 14*4882a593Smuzhiyun #address-cells = <0>; 15*4882a593Smuzhiyun #size-cells = <0>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpu { 18*4882a593Smuzhiyun device_type = "cpu"; 19*4882a593Smuzhiyun compatible = "arm,arm926ej-s"; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun memory { 24*4882a593Smuzhiyun device_type = "memory"; 25*4882a593Smuzhiyun reg = <0x0 0x0>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun aliases { 29*4882a593Smuzhiyun serial0 = &uart0; 30*4882a593Smuzhiyun serial1 = &uart1; 31*4882a593Smuzhiyun serial2 = &uart2; 32*4882a593Smuzhiyun serial3 = &uart3; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun soc { 36*4882a593Smuzhiyun #address-cells = <1>; 37*4882a593Smuzhiyun #size-cells = <1>; 38*4882a593Smuzhiyun compatible = "simple-bus"; 39*4882a593Smuzhiyun ranges; 40*4882a593Smuzhiyun interrupt-parent = <&intc>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun intc: interrupt-controller@d8140000 { 43*4882a593Smuzhiyun compatible = "via,vt8500-intc"; 44*4882a593Smuzhiyun interrupt-controller; 45*4882a593Smuzhiyun reg = <0xd8140000 0x10000>; 46*4882a593Smuzhiyun #interrupt-cells = <1>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun pinctrl: pinctrl@d8110000 { 50*4882a593Smuzhiyun compatible = "via,vt8500-pinctrl"; 51*4882a593Smuzhiyun reg = <0xd8110000 0x10000>; 52*4882a593Smuzhiyun interrupt-controller; 53*4882a593Smuzhiyun #interrupt-cells = <2>; 54*4882a593Smuzhiyun gpio-controller; 55*4882a593Smuzhiyun #gpio-cells = <2>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun pmc@d8130000 { 59*4882a593Smuzhiyun compatible = "via,vt8500-pmc"; 60*4882a593Smuzhiyun reg = <0xd8130000 0x1000>; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun clocks { 63*4882a593Smuzhiyun #address-cells = <1>; 64*4882a593Smuzhiyun #size-cells = <0>; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun ref24: ref24M { 67*4882a593Smuzhiyun #clock-cells = <0>; 68*4882a593Smuzhiyun compatible = "fixed-clock"; 69*4882a593Smuzhiyun clock-frequency = <24000000>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun clkuart0: uart0 { 73*4882a593Smuzhiyun #clock-cells = <0>; 74*4882a593Smuzhiyun compatible = "via,vt8500-device-clock"; 75*4882a593Smuzhiyun clocks = <&ref24>; 76*4882a593Smuzhiyun enable-reg = <0x250>; 77*4882a593Smuzhiyun enable-bit = <1>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun clkuart1: uart1 { 81*4882a593Smuzhiyun #clock-cells = <0>; 82*4882a593Smuzhiyun compatible = "via,vt8500-device-clock"; 83*4882a593Smuzhiyun clocks = <&ref24>; 84*4882a593Smuzhiyun enable-reg = <0x250>; 85*4882a593Smuzhiyun enable-bit = <2>; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun clkuart2: uart2 { 89*4882a593Smuzhiyun #clock-cells = <0>; 90*4882a593Smuzhiyun compatible = "via,vt8500-device-clock"; 91*4882a593Smuzhiyun clocks = <&ref24>; 92*4882a593Smuzhiyun enable-reg = <0x250>; 93*4882a593Smuzhiyun enable-bit = <3>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun clkuart3: uart3 { 97*4882a593Smuzhiyun #clock-cells = <0>; 98*4882a593Smuzhiyun compatible = "via,vt8500-device-clock"; 99*4882a593Smuzhiyun clocks = <&ref24>; 100*4882a593Smuzhiyun enable-reg = <0x250>; 101*4882a593Smuzhiyun enable-bit = <4>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun timer@d8130100 { 107*4882a593Smuzhiyun compatible = "via,vt8500-timer"; 108*4882a593Smuzhiyun reg = <0xd8130100 0x28>; 109*4882a593Smuzhiyun interrupts = <36>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun ehci@d8007900 { 113*4882a593Smuzhiyun compatible = "via,vt8500-ehci"; 114*4882a593Smuzhiyun reg = <0xd8007900 0x200>; 115*4882a593Smuzhiyun interrupts = <43>; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun uhci@d8007b00 { 119*4882a593Smuzhiyun compatible = "platform-uhci"; 120*4882a593Smuzhiyun reg = <0xd8007b00 0x200>; 121*4882a593Smuzhiyun interrupts = <43>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun fb: fb@d8050800 { 125*4882a593Smuzhiyun compatible = "via,vt8500-fb"; 126*4882a593Smuzhiyun reg = <0xd800e400 0x400>; 127*4882a593Smuzhiyun interrupts = <12>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun ge_rops@d8050400 { 131*4882a593Smuzhiyun compatible = "wm,prizm-ge-rops"; 132*4882a593Smuzhiyun reg = <0xd8050400 0x100>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun uart0: serial@d8200000 { 136*4882a593Smuzhiyun compatible = "via,vt8500-uart"; 137*4882a593Smuzhiyun reg = <0xd8200000 0x1040>; 138*4882a593Smuzhiyun interrupts = <32>; 139*4882a593Smuzhiyun clocks = <&clkuart0>; 140*4882a593Smuzhiyun status = "disabled"; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun uart1: serial@d82b0000 { 144*4882a593Smuzhiyun compatible = "via,vt8500-uart"; 145*4882a593Smuzhiyun reg = <0xd82b0000 0x1040>; 146*4882a593Smuzhiyun interrupts = <33>; 147*4882a593Smuzhiyun clocks = <&clkuart1>; 148*4882a593Smuzhiyun status = "disabled"; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun uart2: serial@d8210000 { 152*4882a593Smuzhiyun compatible = "via,vt8500-uart"; 153*4882a593Smuzhiyun reg = <0xd8210000 0x1040>; 154*4882a593Smuzhiyun interrupts = <47>; 155*4882a593Smuzhiyun clocks = <&clkuart2>; 156*4882a593Smuzhiyun status = "disabled"; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun uart3: serial@d82c0000 { 160*4882a593Smuzhiyun compatible = "via,vt8500-uart"; 161*4882a593Smuzhiyun reg = <0xd82c0000 0x1040>; 162*4882a593Smuzhiyun interrupts = <50>; 163*4882a593Smuzhiyun clocks = <&clkuart3>; 164*4882a593Smuzhiyun status = "disabled"; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun rtc@d8100000 { 168*4882a593Smuzhiyun compatible = "via,vt8500-rtc"; 169*4882a593Smuzhiyun reg = <0xd8100000 0x10000>; 170*4882a593Smuzhiyun interrupts = <48>; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun ethernet@d8004000 { 174*4882a593Smuzhiyun compatible = "via,vt8500-rhine"; 175*4882a593Smuzhiyun reg = <0xd8004000 0x100>; 176*4882a593Smuzhiyun interrupts = <10>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun}; 180