1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright 2013 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun#include "vfxxx.dtsi" 6*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/arm-gic.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun #address-cells = <1>; 10*4882a593Smuzhiyun #size-cells = <1>; 11*4882a593Smuzhiyun chosen { }; 12*4882a593Smuzhiyun aliases { }; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun cpus { 15*4882a593Smuzhiyun #address-cells = <1>; 16*4882a593Smuzhiyun #size-cells = <0>; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun a5_cpu: cpu@0 { 19*4882a593Smuzhiyun compatible = "arm,cortex-a5"; 20*4882a593Smuzhiyun device_type = "cpu"; 21*4882a593Smuzhiyun reg = <0x0>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun soc { 26*4882a593Smuzhiyun bus@40000000 { 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun intc: interrupt-controller@40003000 { 29*4882a593Smuzhiyun compatible = "arm,cortex-a9-gic"; 30*4882a593Smuzhiyun #interrupt-cells = <3>; 31*4882a593Smuzhiyun interrupt-controller; 32*4882a593Smuzhiyun interrupt-parent = <&intc>; 33*4882a593Smuzhiyun reg = <0x40003000 0x1000>, 34*4882a593Smuzhiyun <0x40002100 0x100>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun global_timer: timer@40002200 { 38*4882a593Smuzhiyun compatible = "arm,cortex-a9-global-timer"; 39*4882a593Smuzhiyun reg = <0x40002200 0x20>; 40*4882a593Smuzhiyun interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 41*4882a593Smuzhiyun interrupt-parent = <&intc>; 42*4882a593Smuzhiyun clocks = <&clks VF610_CLK_PLATFORM_BUS>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun bus@40080000 { 47*4882a593Smuzhiyun pmu@40089000 { 48*4882a593Smuzhiyun compatible = "arm,cortex-a5-pmu"; 49*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 50*4882a593Smuzhiyun interrupt-affinity = <&a5_cpu>; 51*4882a593Smuzhiyun reg = <0x40089000 0x1000>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun}; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun&mscm_ir { 59*4882a593Smuzhiyun interrupt-parent = <&intc>; 60*4882a593Smuzhiyun}; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun&wdoga5 { 63*4882a593Smuzhiyun status = "okay"; 64*4882a593Smuzhiyun}; 65