xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * ARM Ltd. Versatile Express
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Motherboard Express uATX
6*4882a593Smuzhiyun * V2M-P1
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * HBI-0190D
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
11*4882a593Smuzhiyun * Technical Reference Manual)
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * WARNING! The hardware described in this file is independent from the
14*4882a593Smuzhiyun * original variant (vexpress-v2m.dtsi), but there is a strong
15*4882a593Smuzhiyun * correspondence between the two configurations.
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
18*4882a593Smuzhiyun * CHANGES TO vexpress-v2m.dtsi!
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun/ {
22*4882a593Smuzhiyun	v2m_fixed_3v3: fixed-regulator-0 {
23*4882a593Smuzhiyun		compatible = "regulator-fixed";
24*4882a593Smuzhiyun		regulator-name = "3V3";
25*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
26*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
27*4882a593Smuzhiyun		regulator-always-on;
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	v2m_clk24mhz: clk24mhz {
31*4882a593Smuzhiyun		compatible = "fixed-clock";
32*4882a593Smuzhiyun		#clock-cells = <0>;
33*4882a593Smuzhiyun		clock-frequency = <24000000>;
34*4882a593Smuzhiyun		clock-output-names = "v2m:clk24mhz";
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	v2m_refclk1mhz: refclk1mhz {
38*4882a593Smuzhiyun		compatible = "fixed-clock";
39*4882a593Smuzhiyun		#clock-cells = <0>;
40*4882a593Smuzhiyun		clock-frequency = <1000000>;
41*4882a593Smuzhiyun		clock-output-names = "v2m:refclk1mhz";
42*4882a593Smuzhiyun	};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun	v2m_refclk32khz: refclk32khz {
45*4882a593Smuzhiyun		compatible = "fixed-clock";
46*4882a593Smuzhiyun		#clock-cells = <0>;
47*4882a593Smuzhiyun		clock-frequency = <32768>;
48*4882a593Smuzhiyun		clock-output-names = "v2m:refclk32khz";
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	leds {
52*4882a593Smuzhiyun		compatible = "gpio-leds";
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun		led-1 {
55*4882a593Smuzhiyun			label = "v2m:green:user1";
56*4882a593Smuzhiyun			gpios = <&v2m_led_gpios 0 0>;
57*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
58*4882a593Smuzhiyun		};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun		led-2 {
61*4882a593Smuzhiyun			label = "v2m:green:user2";
62*4882a593Smuzhiyun			gpios = <&v2m_led_gpios 1 0>;
63*4882a593Smuzhiyun			linux,default-trigger = "disk-activity";
64*4882a593Smuzhiyun		};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun		led-3 {
67*4882a593Smuzhiyun			label = "v2m:green:user3";
68*4882a593Smuzhiyun			gpios = <&v2m_led_gpios 2 0>;
69*4882a593Smuzhiyun			linux,default-trigger = "cpu0";
70*4882a593Smuzhiyun		};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun		led-4 {
73*4882a593Smuzhiyun			label = "v2m:green:user4";
74*4882a593Smuzhiyun			gpios = <&v2m_led_gpios 3 0>;
75*4882a593Smuzhiyun			linux,default-trigger = "cpu1";
76*4882a593Smuzhiyun		};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun		led-5 {
79*4882a593Smuzhiyun			label = "v2m:green:user5";
80*4882a593Smuzhiyun			gpios = <&v2m_led_gpios 4 0>;
81*4882a593Smuzhiyun			linux,default-trigger = "cpu2";
82*4882a593Smuzhiyun		};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun		led-6 {
85*4882a593Smuzhiyun			label = "v2m:green:user6";
86*4882a593Smuzhiyun			gpios = <&v2m_led_gpios 5 0>;
87*4882a593Smuzhiyun			linux,default-trigger = "cpu3";
88*4882a593Smuzhiyun		};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun		led-7 {
91*4882a593Smuzhiyun			label = "v2m:green:user7";
92*4882a593Smuzhiyun			gpios = <&v2m_led_gpios 6 0>;
93*4882a593Smuzhiyun			linux,default-trigger = "cpu4";
94*4882a593Smuzhiyun		};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun		led-8 {
97*4882a593Smuzhiyun			label = "v2m:green:user8";
98*4882a593Smuzhiyun			gpios = <&v2m_led_gpios 7 0>;
99*4882a593Smuzhiyun			linux,default-trigger = "cpu5";
100*4882a593Smuzhiyun		};
101*4882a593Smuzhiyun	};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun	bus@8000000 {
104*4882a593Smuzhiyun		motherboard-bus {
105*4882a593Smuzhiyun			model = "V2M-P1";
106*4882a593Smuzhiyun			arm,hbi = <0x190>;
107*4882a593Smuzhiyun			arm,vexpress,site = <0>;
108*4882a593Smuzhiyun			arm,v2m-memory-map = "rs1";
109*4882a593Smuzhiyun			compatible = "arm,vexpress,v2m-p1", "simple-bus";
110*4882a593Smuzhiyun			#address-cells = <2>; /* SMB chipselect number and offset */
111*4882a593Smuzhiyun			#size-cells = <1>;
112*4882a593Smuzhiyun			#interrupt-cells = <1>;
113*4882a593Smuzhiyun			ranges;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun			nor_flash: flash@0 {
116*4882a593Smuzhiyun				compatible = "arm,vexpress-flash", "cfi-flash";
117*4882a593Smuzhiyun				reg = <0 0x00000000 0x04000000>,
118*4882a593Smuzhiyun				      <4 0x00000000 0x04000000>;
119*4882a593Smuzhiyun				bank-width = <4>;
120*4882a593Smuzhiyun				partitions {
121*4882a593Smuzhiyun					compatible = "arm,arm-firmware-suite";
122*4882a593Smuzhiyun				};
123*4882a593Smuzhiyun			};
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun			psram@100000000 {
126*4882a593Smuzhiyun				compatible = "arm,vexpress-psram", "mtd-ram";
127*4882a593Smuzhiyun				reg = <1 0x00000000 0x02000000>;
128*4882a593Smuzhiyun				bank-width = <4>;
129*4882a593Smuzhiyun			};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun			ethernet@202000000 {
132*4882a593Smuzhiyun				compatible = "smsc,lan9118", "smsc,lan9115";
133*4882a593Smuzhiyun				reg = <2 0x02000000 0x10000>;
134*4882a593Smuzhiyun				interrupts = <15>;
135*4882a593Smuzhiyun				phy-mode = "mii";
136*4882a593Smuzhiyun				reg-io-width = <4>;
137*4882a593Smuzhiyun				smsc,irq-active-high;
138*4882a593Smuzhiyun				smsc,irq-push-pull;
139*4882a593Smuzhiyun				vdd33a-supply = <&v2m_fixed_3v3>;
140*4882a593Smuzhiyun				vddvario-supply = <&v2m_fixed_3v3>;
141*4882a593Smuzhiyun			};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun			usb@203000000 {
144*4882a593Smuzhiyun				compatible = "nxp,usb-isp1761";
145*4882a593Smuzhiyun				reg = <2 0x03000000 0x20000>;
146*4882a593Smuzhiyun				interrupts = <16>;
147*4882a593Smuzhiyun				port1-otg;
148*4882a593Smuzhiyun			};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun			iofpga-bus@300000000 {
151*4882a593Smuzhiyun				compatible = "simple-bus";
152*4882a593Smuzhiyun				#address-cells = <1>;
153*4882a593Smuzhiyun				#size-cells = <1>;
154*4882a593Smuzhiyun				ranges = <0 3 0 0x200000>;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun				v2m_sysreg: sysreg@10000 {
157*4882a593Smuzhiyun					compatible = "arm,vexpress-sysreg";
158*4882a593Smuzhiyun					reg = <0x010000 0x1000>;
159*4882a593Smuzhiyun					#address-cells = <1>;
160*4882a593Smuzhiyun					#size-cells = <1>;
161*4882a593Smuzhiyun					ranges = <0 0x10000 0x1000>;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun					v2m_led_gpios: gpio@8 {
164*4882a593Smuzhiyun						compatible = "arm,vexpress-sysreg,sys_led";
165*4882a593Smuzhiyun						reg = <0x008 4>;
166*4882a593Smuzhiyun						gpio-controller;
167*4882a593Smuzhiyun						#gpio-cells = <2>;
168*4882a593Smuzhiyun					};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun					v2m_mmc_gpios: gpio@48 {
171*4882a593Smuzhiyun						compatible = "arm,vexpress-sysreg,sys_mci";
172*4882a593Smuzhiyun						reg = <0x048 4>;
173*4882a593Smuzhiyun						gpio-controller;
174*4882a593Smuzhiyun						#gpio-cells = <2>;
175*4882a593Smuzhiyun					};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun					v2m_flash_gpios: gpio@4c {
178*4882a593Smuzhiyun						compatible = "arm,vexpress-sysreg,sys_flash";
179*4882a593Smuzhiyun						reg = <0x04c 4>;
180*4882a593Smuzhiyun						gpio-controller;
181*4882a593Smuzhiyun						#gpio-cells = <2>;
182*4882a593Smuzhiyun					};
183*4882a593Smuzhiyun				};
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun				v2m_sysctl: sysctl@20000 {
186*4882a593Smuzhiyun					compatible = "arm,sp810", "arm,primecell";
187*4882a593Smuzhiyun					reg = <0x020000 0x1000>;
188*4882a593Smuzhiyun					clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
189*4882a593Smuzhiyun					clock-names = "refclk", "timclk", "apb_pclk";
190*4882a593Smuzhiyun					#clock-cells = <1>;
191*4882a593Smuzhiyun					clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
192*4882a593Smuzhiyun					assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
193*4882a593Smuzhiyun					assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
194*4882a593Smuzhiyun				};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun				/* PCI-E I2C bus */
197*4882a593Smuzhiyun				v2m_i2c_pcie: i2c@30000 {
198*4882a593Smuzhiyun					compatible = "arm,versatile-i2c";
199*4882a593Smuzhiyun					reg = <0x030000 0x1000>;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun					#address-cells = <1>;
202*4882a593Smuzhiyun					#size-cells = <0>;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun					pcie-switch@60 {
205*4882a593Smuzhiyun						compatible = "idt,89hpes32h8";
206*4882a593Smuzhiyun						reg = <0x60>;
207*4882a593Smuzhiyun					};
208*4882a593Smuzhiyun				};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun				aaci@40000 {
211*4882a593Smuzhiyun					compatible = "arm,pl041", "arm,primecell";
212*4882a593Smuzhiyun					reg = <0x040000 0x1000>;
213*4882a593Smuzhiyun					interrupts = <11>;
214*4882a593Smuzhiyun					clocks = <&smbclk>;
215*4882a593Smuzhiyun					clock-names = "apb_pclk";
216*4882a593Smuzhiyun				};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun				mmci@50000 {
219*4882a593Smuzhiyun					compatible = "arm,pl180", "arm,primecell";
220*4882a593Smuzhiyun					reg = <0x050000 0x1000>;
221*4882a593Smuzhiyun					interrupts = <9>, <10>;
222*4882a593Smuzhiyun					cd-gpios = <&v2m_mmc_gpios 0 0>;
223*4882a593Smuzhiyun					wp-gpios = <&v2m_mmc_gpios 1 0>;
224*4882a593Smuzhiyun					max-frequency = <12000000>;
225*4882a593Smuzhiyun					vmmc-supply = <&v2m_fixed_3v3>;
226*4882a593Smuzhiyun					clocks = <&v2m_clk24mhz>, <&smbclk>;
227*4882a593Smuzhiyun					clock-names = "mclk", "apb_pclk";
228*4882a593Smuzhiyun				};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun				kmi@60000 {
231*4882a593Smuzhiyun					compatible = "arm,pl050", "arm,primecell";
232*4882a593Smuzhiyun					reg = <0x060000 0x1000>;
233*4882a593Smuzhiyun					interrupts = <12>;
234*4882a593Smuzhiyun					clocks = <&v2m_clk24mhz>, <&smbclk>;
235*4882a593Smuzhiyun					clock-names = "KMIREFCLK", "apb_pclk";
236*4882a593Smuzhiyun				};
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun				kmi@70000 {
239*4882a593Smuzhiyun					compatible = "arm,pl050", "arm,primecell";
240*4882a593Smuzhiyun					reg = <0x070000 0x1000>;
241*4882a593Smuzhiyun					interrupts = <13>;
242*4882a593Smuzhiyun					clocks = <&v2m_clk24mhz>, <&smbclk>;
243*4882a593Smuzhiyun					clock-names = "KMIREFCLK", "apb_pclk";
244*4882a593Smuzhiyun				};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun				v2m_serial0: serial@90000 {
247*4882a593Smuzhiyun					compatible = "arm,pl011", "arm,primecell";
248*4882a593Smuzhiyun					reg = <0x090000 0x1000>;
249*4882a593Smuzhiyun					interrupts = <5>;
250*4882a593Smuzhiyun					clocks = <&v2m_oscclk2>, <&smbclk>;
251*4882a593Smuzhiyun					clock-names = "uartclk", "apb_pclk";
252*4882a593Smuzhiyun				};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun				v2m_serial1: serial@a0000 {
255*4882a593Smuzhiyun					compatible = "arm,pl011", "arm,primecell";
256*4882a593Smuzhiyun					reg = <0x0a0000 0x1000>;
257*4882a593Smuzhiyun					interrupts = <6>;
258*4882a593Smuzhiyun					clocks = <&v2m_oscclk2>, <&smbclk>;
259*4882a593Smuzhiyun					clock-names = "uartclk", "apb_pclk";
260*4882a593Smuzhiyun				};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun				v2m_serial2: serial@b0000 {
263*4882a593Smuzhiyun					compatible = "arm,pl011", "arm,primecell";
264*4882a593Smuzhiyun					reg = <0x0b0000 0x1000>;
265*4882a593Smuzhiyun					interrupts = <7>;
266*4882a593Smuzhiyun					clocks = <&v2m_oscclk2>, <&smbclk>;
267*4882a593Smuzhiyun					clock-names = "uartclk", "apb_pclk";
268*4882a593Smuzhiyun				};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun				v2m_serial3: serial@c0000 {
271*4882a593Smuzhiyun					compatible = "arm,pl011", "arm,primecell";
272*4882a593Smuzhiyun					reg = <0x0c0000 0x1000>;
273*4882a593Smuzhiyun					interrupts = <8>;
274*4882a593Smuzhiyun					clocks = <&v2m_oscclk2>, <&smbclk>;
275*4882a593Smuzhiyun					clock-names = "uartclk", "apb_pclk";
276*4882a593Smuzhiyun				};
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun				wdt@f0000 {
279*4882a593Smuzhiyun					compatible = "arm,sp805", "arm,primecell";
280*4882a593Smuzhiyun					reg = <0x0f0000 0x1000>;
281*4882a593Smuzhiyun					interrupts = <0>;
282*4882a593Smuzhiyun					clocks = <&v2m_refclk32khz>, <&smbclk>;
283*4882a593Smuzhiyun					clock-names = "wdog_clk", "apb_pclk";
284*4882a593Smuzhiyun				};
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun				v2m_timer01: timer@110000 {
287*4882a593Smuzhiyun					compatible = "arm,sp804", "arm,primecell";
288*4882a593Smuzhiyun					reg = <0x110000 0x1000>;
289*4882a593Smuzhiyun					interrupts = <2>;
290*4882a593Smuzhiyun					clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
291*4882a593Smuzhiyun					clock-names = "timclken1", "timclken2", "apb_pclk";
292*4882a593Smuzhiyun				};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun				v2m_timer23: timer@120000 {
295*4882a593Smuzhiyun					compatible = "arm,sp804", "arm,primecell";
296*4882a593Smuzhiyun					reg = <0x120000 0x1000>;
297*4882a593Smuzhiyun					interrupts = <3>;
298*4882a593Smuzhiyun					clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
299*4882a593Smuzhiyun					clock-names = "timclken1", "timclken2", "apb_pclk";
300*4882a593Smuzhiyun				};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun				/* DVI I2C bus */
303*4882a593Smuzhiyun				v2m_i2c_dvi: i2c@160000 {
304*4882a593Smuzhiyun					compatible = "arm,versatile-i2c";
305*4882a593Smuzhiyun					reg = <0x160000 0x1000>;
306*4882a593Smuzhiyun					#address-cells = <1>;
307*4882a593Smuzhiyun					#size-cells = <0>;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun					dvi-transmitter@39 {
310*4882a593Smuzhiyun						compatible = "sil,sii9022-tpi", "sil,sii9022";
311*4882a593Smuzhiyun						reg = <0x39>;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun						ports {
314*4882a593Smuzhiyun							#address-cells = <1>;
315*4882a593Smuzhiyun							#size-cells = <0>;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun							port@0 {
318*4882a593Smuzhiyun								reg = <0>;
319*4882a593Smuzhiyun								dvi_bridge_in: endpoint {
320*4882a593Smuzhiyun									remote-endpoint = <&clcd_pads>;
321*4882a593Smuzhiyun								};
322*4882a593Smuzhiyun							};
323*4882a593Smuzhiyun						};
324*4882a593Smuzhiyun					};
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun					dvi-transmitter@60 {
327*4882a593Smuzhiyun						compatible = "sil,sii9022-cpi", "sil,sii9022";
328*4882a593Smuzhiyun						reg = <0x60>;
329*4882a593Smuzhiyun					};
330*4882a593Smuzhiyun				};
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun				rtc@170000 {
333*4882a593Smuzhiyun					compatible = "arm,pl031", "arm,primecell";
334*4882a593Smuzhiyun					reg = <0x170000 0x1000>;
335*4882a593Smuzhiyun					interrupts = <4>;
336*4882a593Smuzhiyun					clocks = <&smbclk>;
337*4882a593Smuzhiyun					clock-names = "apb_pclk";
338*4882a593Smuzhiyun				};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun				compact-flash@1a0000 {
341*4882a593Smuzhiyun					compatible = "arm,vexpress-cf", "ata-generic";
342*4882a593Smuzhiyun					reg = <0x1a0000 0x100
343*4882a593Smuzhiyun					       0x1a0100 0xf00>;
344*4882a593Smuzhiyun					reg-shift = <2>;
345*4882a593Smuzhiyun				};
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun				clcd@1f0000 {
348*4882a593Smuzhiyun					compatible = "arm,pl111", "arm,primecell";
349*4882a593Smuzhiyun					reg = <0x1f0000 0x1000>;
350*4882a593Smuzhiyun					interrupt-names = "combined";
351*4882a593Smuzhiyun					interrupts = <14>;
352*4882a593Smuzhiyun					clocks = <&v2m_oscclk1>, <&smbclk>;
353*4882a593Smuzhiyun					clock-names = "clcdclk", "apb_pclk";
354*4882a593Smuzhiyun					/* 800x600 16bpp @36MHz works fine */
355*4882a593Smuzhiyun					max-memory-bandwidth = <54000000>;
356*4882a593Smuzhiyun					memory-region = <&vram>;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun					port {
359*4882a593Smuzhiyun						clcd_pads: endpoint {
360*4882a593Smuzhiyun							remote-endpoint = <&dvi_bridge_in>;
361*4882a593Smuzhiyun							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
362*4882a593Smuzhiyun						};
363*4882a593Smuzhiyun					};
364*4882a593Smuzhiyun				};
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun				mcc {
367*4882a593Smuzhiyun					compatible = "arm,vexpress,config-bus";
368*4882a593Smuzhiyun					arm,vexpress,config-bridge = <&v2m_sysreg>;
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun					oscclk0 {
371*4882a593Smuzhiyun						/* MCC static memory clock */
372*4882a593Smuzhiyun						compatible = "arm,vexpress-osc";
373*4882a593Smuzhiyun						arm,vexpress-sysreg,func = <1 0>;
374*4882a593Smuzhiyun						freq-range = <25000000 60000000>;
375*4882a593Smuzhiyun						#clock-cells = <0>;
376*4882a593Smuzhiyun						clock-output-names = "v2m:oscclk0";
377*4882a593Smuzhiyun					};
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun					v2m_oscclk1: oscclk1 {
380*4882a593Smuzhiyun						/* CLCD clock */
381*4882a593Smuzhiyun						compatible = "arm,vexpress-osc";
382*4882a593Smuzhiyun						arm,vexpress-sysreg,func = <1 1>;
383*4882a593Smuzhiyun						freq-range = <23750000 65000000>;
384*4882a593Smuzhiyun						#clock-cells = <0>;
385*4882a593Smuzhiyun						clock-output-names = "v2m:oscclk1";
386*4882a593Smuzhiyun					};
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun					v2m_oscclk2: oscclk2 {
389*4882a593Smuzhiyun						/* IO FPGA peripheral clock */
390*4882a593Smuzhiyun						compatible = "arm,vexpress-osc";
391*4882a593Smuzhiyun						arm,vexpress-sysreg,func = <1 2>;
392*4882a593Smuzhiyun						freq-range = <24000000 24000000>;
393*4882a593Smuzhiyun						#clock-cells = <0>;
394*4882a593Smuzhiyun						clock-output-names = "v2m:oscclk2";
395*4882a593Smuzhiyun					};
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun					volt-vio {
398*4882a593Smuzhiyun						/* Logic level voltage */
399*4882a593Smuzhiyun						compatible = "arm,vexpress-volt";
400*4882a593Smuzhiyun						arm,vexpress-sysreg,func = <2 0>;
401*4882a593Smuzhiyun						regulator-name = "VIO";
402*4882a593Smuzhiyun						regulator-always-on;
403*4882a593Smuzhiyun						label = "VIO";
404*4882a593Smuzhiyun					};
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun					temp-mcc {
407*4882a593Smuzhiyun						/* MCC internal operating temperature */
408*4882a593Smuzhiyun						compatible = "arm,vexpress-temp";
409*4882a593Smuzhiyun						arm,vexpress-sysreg,func = <4 0>;
410*4882a593Smuzhiyun						label = "MCC";
411*4882a593Smuzhiyun					};
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun					reset {
414*4882a593Smuzhiyun						compatible = "arm,vexpress-reset";
415*4882a593Smuzhiyun						arm,vexpress-sysreg,func = <5 0>;
416*4882a593Smuzhiyun					};
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun					muxfpga {
419*4882a593Smuzhiyun						compatible = "arm,vexpress-muxfpga";
420*4882a593Smuzhiyun						arm,vexpress-sysreg,func = <7 0>;
421*4882a593Smuzhiyun					};
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun					shutdown {
424*4882a593Smuzhiyun						compatible = "arm,vexpress-shutdown";
425*4882a593Smuzhiyun						arm,vexpress-sysreg,func = <8 0>;
426*4882a593Smuzhiyun					};
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun					reboot {
429*4882a593Smuzhiyun						compatible = "arm,vexpress-reboot";
430*4882a593Smuzhiyun						arm,vexpress-sysreg,func = <9 0>;
431*4882a593Smuzhiyun					};
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun					dvimode {
434*4882a593Smuzhiyun						compatible = "arm,vexpress-dvimode";
435*4882a593Smuzhiyun						arm,vexpress-sysreg,func = <11 0>;
436*4882a593Smuzhiyun					};
437*4882a593Smuzhiyun				};
438*4882a593Smuzhiyun			};
439*4882a593Smuzhiyun		};
440*4882a593Smuzhiyun	};
441*4882a593Smuzhiyun};
442