1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun#include "versatile-ab.dts" 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun/ { 5*4882a593Smuzhiyun model = "ARM Versatile PB"; 6*4882a593Smuzhiyun compatible = "arm,versatile-pb"; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun amba { 9*4882a593Smuzhiyun /* The Versatile PB is using more SIC IRQ lines than the AB */ 10*4882a593Smuzhiyun sic: interrupt-controller@10003000 { 11*4882a593Smuzhiyun clear-mask = <0xffffffff>; 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Valid interrupt lines mask according to 14*4882a593Smuzhiyun * figure 3-30 page 3-74 of ARM DUI 0224B 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun valid-mask = <0x7fe003ff>; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun gpio2: gpio@101e6000 { 20*4882a593Smuzhiyun compatible = "arm,pl061", "arm,primecell"; 21*4882a593Smuzhiyun reg = <0x101e6000 0x1000>; 22*4882a593Smuzhiyun interrupts = <8>; 23*4882a593Smuzhiyun gpio-controller; 24*4882a593Smuzhiyun #gpio-cells = <2>; 25*4882a593Smuzhiyun interrupt-controller; 26*4882a593Smuzhiyun #interrupt-cells = <2>; 27*4882a593Smuzhiyun clocks = <&pclk>; 28*4882a593Smuzhiyun clock-names = "apb_pclk"; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun gpio3: gpio@101e7000 { 32*4882a593Smuzhiyun compatible = "arm,pl061", "arm,primecell"; 33*4882a593Smuzhiyun reg = <0x101e7000 0x1000>; 34*4882a593Smuzhiyun interrupts = <9>; 35*4882a593Smuzhiyun gpio-controller; 36*4882a593Smuzhiyun #gpio-cells = <2>; 37*4882a593Smuzhiyun interrupt-controller; 38*4882a593Smuzhiyun #interrupt-cells = <2>; 39*4882a593Smuzhiyun clocks = <&pclk>; 40*4882a593Smuzhiyun clock-names = "apb_pclk"; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun pci@10001000 { 44*4882a593Smuzhiyun compatible = "arm,versatile-pci"; 45*4882a593Smuzhiyun device_type = "pci"; 46*4882a593Smuzhiyun reg = <0x10001000 0x1000 47*4882a593Smuzhiyun 0x41000000 0x10000 48*4882a593Smuzhiyun 0x42000000 0x100000>; 49*4882a593Smuzhiyun bus-range = <0 0xff>; 50*4882a593Smuzhiyun #address-cells = <3>; 51*4882a593Smuzhiyun #size-cells = <2>; 52*4882a593Smuzhiyun #interrupt-cells = <1>; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */ 55*4882a593Smuzhiyun 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */ 56*4882a593Smuzhiyun 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun interrupt-map-mask = <0x1800 0 0 7>; 59*4882a593Smuzhiyun interrupt-map = <0x1800 0 0 1 &sic 28 60*4882a593Smuzhiyun 0x1800 0 0 2 &sic 29 61*4882a593Smuzhiyun 0x1800 0 0 3 &sic 30 62*4882a593Smuzhiyun 0x1800 0 0 4 &sic 27 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun 0x1000 0 0 1 &sic 27 65*4882a593Smuzhiyun 0x1000 0 0 2 &sic 28 66*4882a593Smuzhiyun 0x1000 0 0 3 &sic 29 67*4882a593Smuzhiyun 0x1000 0 0 4 &sic 30 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun 0x0800 0 0 1 &sic 30 70*4882a593Smuzhiyun 0x0800 0 0 2 &sic 27 71*4882a593Smuzhiyun 0x0800 0 0 3 &sic 28 72*4882a593Smuzhiyun 0x0800 0 0 4 &sic 29 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun 0x0000 0 0 1 &sic 29 75*4882a593Smuzhiyun 0x0000 0 0 2 &sic 30 76*4882a593Smuzhiyun 0x0000 0 0 3 &sic 27 77*4882a593Smuzhiyun 0x0000 0 0 4 &sic 28>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun fpga { 81*4882a593Smuzhiyun mmc@5000 { 82*4882a593Smuzhiyun /* 83*4882a593Smuzhiyun * Overrides the interrupt assignment from 84*4882a593Smuzhiyun * the Versatile AB board file. 85*4882a593Smuzhiyun */ 86*4882a593Smuzhiyun interrupts-extended = <&sic 22 &sic 23>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun uart@9000 { 89*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 90*4882a593Smuzhiyun reg = <0x9000 0x1000>; 91*4882a593Smuzhiyun interrupt-parent = <&sic>; 92*4882a593Smuzhiyun interrupts = <6>; 93*4882a593Smuzhiyun clocks = <&xtal24mhz>, <&pclk>; 94*4882a593Smuzhiyun clock-names = "uartclk", "apb_pclk"; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun sci@a000 { 97*4882a593Smuzhiyun compatible = "arm,primecell"; 98*4882a593Smuzhiyun reg = <0xa000 0x1000>; 99*4882a593Smuzhiyun interrupt-parent = <&sic>; 100*4882a593Smuzhiyun interrupts = <5>; 101*4882a593Smuzhiyun clocks = <&xtal24mhz>; 102*4882a593Smuzhiyun clock-names = "apb_pclk"; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun mmc@b000 { 105*4882a593Smuzhiyun compatible = "arm,pl180", "arm,primecell"; 106*4882a593Smuzhiyun reg = <0xb000 0x1000>; 107*4882a593Smuzhiyun interrupt-parent = <&sic>; 108*4882a593Smuzhiyun interrupts = <1>, <2>; 109*4882a593Smuzhiyun clocks = <&xtal24mhz>, <&pclk>; 110*4882a593Smuzhiyun clock-names = "mclk", "apb_pclk"; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun}; 115