1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun#include <dt-bindings/input/gpio-keys.h> 4*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 5*4882a593Smuzhiyun#include <dt-bindings/power/summit,smb347-charger.h> 6*4882a593Smuzhiyun#include <dt-bindings/thermal/thermal.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "tegra30.dtsi" 9*4882a593Smuzhiyun#include "tegra30-cpu-opp.dtsi" 10*4882a593Smuzhiyun#include "tegra30-cpu-opp-microvolt.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun aliases { 14*4882a593Smuzhiyun mmc0 = &sdmmc4; /* eMMC */ 15*4882a593Smuzhiyun mmc1 = &sdmmc3; /* WiFi */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun rtc0 = &pmic; 18*4882a593Smuzhiyun rtc1 = "/rtc@7000e000"; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun serial1 = &uartc; /* Bluetooth */ 21*4882a593Smuzhiyun serial2 = &uartb; /* GPS */ 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * The decompressor and also some bootloaders rely on a 26*4882a593Smuzhiyun * pre-existing /chosen node to be available to insert the 27*4882a593Smuzhiyun * command line and merge other ATAGS info. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun chosen {}; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun memory@80000000 { 32*4882a593Smuzhiyun reg = <0x80000000 0x40000000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun reserved-memory { 36*4882a593Smuzhiyun #address-cells = <1>; 37*4882a593Smuzhiyun #size-cells = <1>; 38*4882a593Smuzhiyun ranges; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun linux,cma@80000000 { 41*4882a593Smuzhiyun compatible = "shared-dma-pool"; 42*4882a593Smuzhiyun alloc-ranges = <0x80000000 0x30000000>; 43*4882a593Smuzhiyun size = <0x10000000>; /* 256MiB */ 44*4882a593Smuzhiyun linux,cma-default; 45*4882a593Smuzhiyun reusable; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun ramoops@bfdf0000 { 49*4882a593Smuzhiyun compatible = "ramoops"; 50*4882a593Smuzhiyun reg = <0xbfdf0000 0x10000>; /* 64kB */ 51*4882a593Smuzhiyun console-size = <0x8000>; /* 32kB */ 52*4882a593Smuzhiyun record-size = <0x400>; /* 1kB */ 53*4882a593Smuzhiyun ecc-size = <16>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun trustzone@bfe00000 { 57*4882a593Smuzhiyun reg = <0xbfe00000 0x200000>; 58*4882a593Smuzhiyun no-map; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun host1x@50000000 { 63*4882a593Smuzhiyun dc@54200000 { 64*4882a593Smuzhiyun rgb { 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun port@0 { 68*4882a593Smuzhiyun lcd_output: endpoint { 69*4882a593Smuzhiyun remote-endpoint = <&lvds_encoder_input>; 70*4882a593Smuzhiyun bus-width = <24>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun gpio@6000d000 { 78*4882a593Smuzhiyun init-mode { 79*4882a593Smuzhiyun gpio-hog; 80*4882a593Smuzhiyun gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>, 81*4882a593Smuzhiyun <TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>, 82*4882a593Smuzhiyun <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 83*4882a593Smuzhiyun output-low; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun init-low-power-mode { 87*4882a593Smuzhiyun gpio-hog; 88*4882a593Smuzhiyun gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 89*4882a593Smuzhiyun input; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun pinmux@70000868 { 94*4882a593Smuzhiyun pinctrl-names = "default"; 95*4882a593Smuzhiyun pinctrl-0 = <&state_default>; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun state_default: pinmux { 98*4882a593Smuzhiyun clk_32k_out_pa0 { 99*4882a593Smuzhiyun nvidia,pins = "clk_32k_out_pa0"; 100*4882a593Smuzhiyun nvidia,function = "blink"; 101*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 102*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 103*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun uart3_cts_n_pa1 { 106*4882a593Smuzhiyun nvidia,pins = "uart3_cts_n_pa1", 107*4882a593Smuzhiyun "uart3_rxd_pw7"; 108*4882a593Smuzhiyun nvidia,function = "uartc"; 109*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 110*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 111*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun dap2_fs_pa2 { 114*4882a593Smuzhiyun nvidia,pins = "dap2_fs_pa2", 115*4882a593Smuzhiyun "dap2_sclk_pa3", 116*4882a593Smuzhiyun "dap2_din_pa4", 117*4882a593Smuzhiyun "dap2_dout_pa5"; 118*4882a593Smuzhiyun nvidia,function = "i2s1"; 119*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 120*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 121*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun sdmmc3_clk_pa6 { 124*4882a593Smuzhiyun nvidia,pins = "sdmmc3_clk_pa6"; 125*4882a593Smuzhiyun nvidia,function = "sdmmc3"; 126*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 127*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 128*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun sdmmc3_cmd_pa7 { 131*4882a593Smuzhiyun nvidia,pins = "sdmmc3_cmd_pa7", 132*4882a593Smuzhiyun "sdmmc3_dat3_pb4", 133*4882a593Smuzhiyun "sdmmc3_dat2_pb5", 134*4882a593Smuzhiyun "sdmmc3_dat1_pb6", 135*4882a593Smuzhiyun "sdmmc3_dat0_pb7", 136*4882a593Smuzhiyun "sdmmc3_dat4_pd1", 137*4882a593Smuzhiyun "sdmmc3_dat6_pd3", 138*4882a593Smuzhiyun "sdmmc3_dat7_pd4"; 139*4882a593Smuzhiyun nvidia,function = "sdmmc3"; 140*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 141*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 142*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun gmi_a17_pb0 { 145*4882a593Smuzhiyun nvidia,pins = "gmi_a17_pb0", 146*4882a593Smuzhiyun "gmi_a18_pb1"; 147*4882a593Smuzhiyun nvidia,function = "uartd"; 148*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 149*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 150*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun lcd_pwr0_pb2 { 153*4882a593Smuzhiyun nvidia,pins = "lcd_pwr0_pb2", 154*4882a593Smuzhiyun "lcd_pwr1_pc1", 155*4882a593Smuzhiyun "lcd_m1_pw1"; 156*4882a593Smuzhiyun nvidia,function = "displaya"; 157*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 158*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 159*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun lcd_pclk_pb3 { 162*4882a593Smuzhiyun nvidia,pins = "lcd_pclk_pb3", 163*4882a593Smuzhiyun "lcd_d0_pe0", 164*4882a593Smuzhiyun "lcd_d1_pe1", 165*4882a593Smuzhiyun "lcd_d2_pe2", 166*4882a593Smuzhiyun "lcd_d3_pe3", 167*4882a593Smuzhiyun "lcd_d4_pe4", 168*4882a593Smuzhiyun "lcd_d5_pe5", 169*4882a593Smuzhiyun "lcd_d6_pe6", 170*4882a593Smuzhiyun "lcd_d7_pe7", 171*4882a593Smuzhiyun "lcd_d8_pf0", 172*4882a593Smuzhiyun "lcd_d9_pf1", 173*4882a593Smuzhiyun "lcd_d10_pf2", 174*4882a593Smuzhiyun "lcd_d11_pf3", 175*4882a593Smuzhiyun "lcd_d12_pf4", 176*4882a593Smuzhiyun "lcd_d13_pf5", 177*4882a593Smuzhiyun "lcd_d14_pf6", 178*4882a593Smuzhiyun "lcd_d15_pf7", 179*4882a593Smuzhiyun "lcd_de_pj1", 180*4882a593Smuzhiyun "lcd_hsync_pj3", 181*4882a593Smuzhiyun "lcd_vsync_pj4", 182*4882a593Smuzhiyun "lcd_d16_pm0", 183*4882a593Smuzhiyun "lcd_d17_pm1", 184*4882a593Smuzhiyun "lcd_d18_pm2", 185*4882a593Smuzhiyun "lcd_d19_pm3", 186*4882a593Smuzhiyun "lcd_d20_pm4", 187*4882a593Smuzhiyun "lcd_d21_pm5", 188*4882a593Smuzhiyun "lcd_d22_pm6", 189*4882a593Smuzhiyun "lcd_d23_pm7", 190*4882a593Smuzhiyun "lcd_cs0_n_pn4", 191*4882a593Smuzhiyun "lcd_sdout_pn5", 192*4882a593Smuzhiyun "lcd_dc0_pn6", 193*4882a593Smuzhiyun "lcd_cs1_n_pw0", 194*4882a593Smuzhiyun "lcd_sdin_pz2", 195*4882a593Smuzhiyun "lcd_sck_pz4"; 196*4882a593Smuzhiyun nvidia,function = "displaya"; 197*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 198*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 199*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun uart3_rts_n_pc0 { 202*4882a593Smuzhiyun nvidia,pins = "uart3_rts_n_pc0", 203*4882a593Smuzhiyun "uart3_txd_pw6"; 204*4882a593Smuzhiyun nvidia,function = "uartc"; 205*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 206*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 207*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun uart2_txd_pc2 { 210*4882a593Smuzhiyun nvidia,pins = "uart2_txd_pc2", 211*4882a593Smuzhiyun "uart2_rts_n_pj6"; 212*4882a593Smuzhiyun nvidia,function = "uartb"; 213*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 214*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 215*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun uart2_rxd_pc3 { 218*4882a593Smuzhiyun nvidia,pins = "uart2_rxd_pc3", 219*4882a593Smuzhiyun "uart2_cts_n_pj5"; 220*4882a593Smuzhiyun nvidia,function = "uartb"; 221*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 222*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 223*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun gen1_i2c_scl_pc4 { 226*4882a593Smuzhiyun nvidia,pins = "gen1_i2c_scl_pc4", 227*4882a593Smuzhiyun "gen1_i2c_sda_pc5"; 228*4882a593Smuzhiyun nvidia,function = "i2c1"; 229*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 230*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 231*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 232*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_ENABLE>; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun gmi_wp_n_pc7 { 235*4882a593Smuzhiyun nvidia,pins = "gmi_wp_n_pc7", 236*4882a593Smuzhiyun "gmi_wait_pi7", 237*4882a593Smuzhiyun "gmi_cs4_n_pk2", 238*4882a593Smuzhiyun "gmi_cs3_n_pk4"; 239*4882a593Smuzhiyun nvidia,function = "rsvd1"; 240*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 241*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 242*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun gmi_ad12_ph4 { 245*4882a593Smuzhiyun nvidia,pins = "gmi_ad12_ph4", 246*4882a593Smuzhiyun "gmi_cs0_n_pj0", 247*4882a593Smuzhiyun "gmi_cs1_n_pj2", 248*4882a593Smuzhiyun "gmi_cs2_n_pk3"; 249*4882a593Smuzhiyun nvidia,function = "rsvd1"; 250*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 251*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 252*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun sdmmc3_dat5_pd0 { 255*4882a593Smuzhiyun nvidia,pins = "sdmmc3_dat5_pd0"; 256*4882a593Smuzhiyun nvidia,function = "sdmmc3"; 257*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 258*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 259*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun gmi_ad0_pg0 { 262*4882a593Smuzhiyun nvidia,pins = "gmi_ad0_pg0", 263*4882a593Smuzhiyun "gmi_ad1_pg1", 264*4882a593Smuzhiyun "gmi_ad14_ph6", 265*4882a593Smuzhiyun "pu1"; 266*4882a593Smuzhiyun nvidia,function = "rsvd1"; 267*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 268*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 269*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun gmi_ad2_pg2 { 272*4882a593Smuzhiyun nvidia,pins = "gmi_ad2_pg2", 273*4882a593Smuzhiyun "gmi_ad3_pg3", 274*4882a593Smuzhiyun "gmi_ad6_pg6", 275*4882a593Smuzhiyun "gmi_ad7_pg7"; 276*4882a593Smuzhiyun nvidia,function = "rsvd1"; 277*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 278*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 279*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun gmi_ad4_pg4 { 282*4882a593Smuzhiyun nvidia,pins = "gmi_ad4_pg4", 283*4882a593Smuzhiyun "gmi_ad5_pg5"; 284*4882a593Smuzhiyun nvidia,function = "nand"; 285*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 286*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 287*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun gmi_ad8_ph0 { 290*4882a593Smuzhiyun nvidia,pins = "gmi_ad8_ph0"; 291*4882a593Smuzhiyun nvidia,function = "pwm0"; 292*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 293*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 294*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 295*4882a593Smuzhiyun }; 296*4882a593Smuzhiyun gmi_ad9_ph1 { 297*4882a593Smuzhiyun nvidia,pins = "gmi_ad9_ph1"; 298*4882a593Smuzhiyun nvidia,function = "rsvd4"; 299*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 300*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 301*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 302*4882a593Smuzhiyun }; 303*4882a593Smuzhiyun gmi_ad10_ph2 { 304*4882a593Smuzhiyun nvidia,pins = "gmi_ad10_ph2"; 305*4882a593Smuzhiyun nvidia,function = "pwm2"; 306*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 307*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 308*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun gmi_ad11_ph3 { 311*4882a593Smuzhiyun nvidia,pins = "gmi_ad11_ph3"; 312*4882a593Smuzhiyun nvidia,function = "pwm3"; 313*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 314*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 315*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun gmi_ad13_ph5 { 318*4882a593Smuzhiyun nvidia,pins = "gmi_ad13_ph5", 319*4882a593Smuzhiyun "gmi_wr_n_pi0", 320*4882a593Smuzhiyun "gmi_oe_n_pi1", 321*4882a593Smuzhiyun "gmi_adv_n_pk0"; 322*4882a593Smuzhiyun nvidia,function = "rsvd1"; 323*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 324*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 325*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun gmi_ad15_ph7 { 328*4882a593Smuzhiyun nvidia,pins = "gmi_ad15_ph7"; 329*4882a593Smuzhiyun nvidia,function = "rsvd1"; 330*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 331*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 332*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 333*4882a593Smuzhiyun }; 334*4882a593Smuzhiyun gmi_dqs_pi2 { 335*4882a593Smuzhiyun nvidia,pins = "gmi_dqs_pi2", 336*4882a593Smuzhiyun "pu2", 337*4882a593Smuzhiyun "pv1"; 338*4882a593Smuzhiyun nvidia,function = "rsvd1"; 339*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 340*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 341*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun gmi_rst_n_pi4 { 344*4882a593Smuzhiyun nvidia,pins = "gmi_rst_n_pi4"; 345*4882a593Smuzhiyun nvidia,function = "nand"; 346*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 347*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 348*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 349*4882a593Smuzhiyun }; 350*4882a593Smuzhiyun gmi_iordy_pi5 { 351*4882a593Smuzhiyun nvidia,pins = "gmi_iordy_pi5"; 352*4882a593Smuzhiyun nvidia,function = "rsvd1"; 353*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 354*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 355*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 356*4882a593Smuzhiyun }; 357*4882a593Smuzhiyun gmi_cs7_n_pi6 { 358*4882a593Smuzhiyun nvidia,pins = "gmi_cs7_n_pi6", 359*4882a593Smuzhiyun "gmi_clk_pk1"; 360*4882a593Smuzhiyun nvidia,function = "nand"; 361*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 362*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 363*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun gmi_a16_pj7 { 366*4882a593Smuzhiyun nvidia,pins = "gmi_a16_pj7", 367*4882a593Smuzhiyun "gmi_a19_pk7"; 368*4882a593Smuzhiyun nvidia,function = "uartd"; 369*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 370*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 371*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 372*4882a593Smuzhiyun }; 373*4882a593Smuzhiyun spdif_out_pk5 { 374*4882a593Smuzhiyun nvidia,pins = "spdif_out_pk5"; 375*4882a593Smuzhiyun nvidia,function = "spdif"; 376*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 377*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 378*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 379*4882a593Smuzhiyun }; 380*4882a593Smuzhiyun spdif_in_pk6 { 381*4882a593Smuzhiyun nvidia,pins = "spdif_in_pk6"; 382*4882a593Smuzhiyun nvidia,function = "spdif"; 383*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 384*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 385*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun dap1_fs_pn0 { 388*4882a593Smuzhiyun nvidia,pins = "dap1_fs_pn0", 389*4882a593Smuzhiyun "dap1_din_pn1", 390*4882a593Smuzhiyun "dap1_dout_pn2", 391*4882a593Smuzhiyun "dap1_sclk_pn3"; 392*4882a593Smuzhiyun nvidia,function = "i2s0"; 393*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 394*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 395*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 396*4882a593Smuzhiyun }; 397*4882a593Smuzhiyun hdmi_int_pn7 { 398*4882a593Smuzhiyun nvidia,pins = "hdmi_int_pn7"; 399*4882a593Smuzhiyun nvidia,function = "hdmi"; 400*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 401*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 402*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun ulpi_data7_po0 { 405*4882a593Smuzhiyun nvidia,pins = "ulpi_data7_po0"; 406*4882a593Smuzhiyun nvidia,function = "uarta"; 407*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 408*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 409*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 410*4882a593Smuzhiyun }; 411*4882a593Smuzhiyun ulpi_data3_po4 { 412*4882a593Smuzhiyun nvidia,pins = "ulpi_data3_po4"; 413*4882a593Smuzhiyun nvidia,function = "ulpi"; 414*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 415*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 416*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 417*4882a593Smuzhiyun }; 418*4882a593Smuzhiyun dap3_fs_pp0 { 419*4882a593Smuzhiyun nvidia,pins = "dap3_fs_pp0"; 420*4882a593Smuzhiyun nvidia,function = "i2s2"; 421*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 422*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 423*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 424*4882a593Smuzhiyun }; 425*4882a593Smuzhiyun dap4_fs_pp4 { 426*4882a593Smuzhiyun nvidia,pins = "dap4_fs_pp4", 427*4882a593Smuzhiyun "dap4_din_pp5", 428*4882a593Smuzhiyun "dap4_dout_pp6", 429*4882a593Smuzhiyun "dap4_sclk_pp7"; 430*4882a593Smuzhiyun nvidia,function = "i2s3"; 431*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 432*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 433*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun kb_col0_pq0 { 436*4882a593Smuzhiyun nvidia,pins = "kb_col0_pq0", 437*4882a593Smuzhiyun "kb_col1_pq1", 438*4882a593Smuzhiyun "kb_row1_pr1"; 439*4882a593Smuzhiyun nvidia,function = "kbc"; 440*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 441*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 442*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 443*4882a593Smuzhiyun }; 444*4882a593Smuzhiyun kb_col2_pq2 { 445*4882a593Smuzhiyun nvidia,pins = "kb_col2_pq2", 446*4882a593Smuzhiyun "kb_col3_pq3"; 447*4882a593Smuzhiyun nvidia,function = "rsvd4"; 448*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 449*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 450*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 451*4882a593Smuzhiyun }; 452*4882a593Smuzhiyun kb_col4_pq4 { 453*4882a593Smuzhiyun nvidia,pins = "kb_col4_pq4", 454*4882a593Smuzhiyun "kb_col5_pq5", 455*4882a593Smuzhiyun "kb_col7_pq7", 456*4882a593Smuzhiyun "kb_row2_pr2", 457*4882a593Smuzhiyun "kb_row4_pr4", 458*4882a593Smuzhiyun "kb_row5_pr5", 459*4882a593Smuzhiyun "kb_row14_ps6"; 460*4882a593Smuzhiyun nvidia,function = "kbc"; 461*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 462*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 463*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 464*4882a593Smuzhiyun }; 465*4882a593Smuzhiyun kb_row0_pr0 { 466*4882a593Smuzhiyun nvidia,pins = "kb_row0_pr0"; 467*4882a593Smuzhiyun nvidia,function = "rsvd4"; 468*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 469*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 470*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun kb_row6_pr6 { 473*4882a593Smuzhiyun nvidia,pins = "kb_row6_pr6", 474*4882a593Smuzhiyun "kb_row8_ps0", 475*4882a593Smuzhiyun "kb_row9_ps1", 476*4882a593Smuzhiyun "kb_row10_ps2"; 477*4882a593Smuzhiyun nvidia,function = "kbc"; 478*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 479*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 480*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 481*4882a593Smuzhiyun }; 482*4882a593Smuzhiyun kb_row11_ps3 { 483*4882a593Smuzhiyun nvidia,pins = "kb_row11_ps3", 484*4882a593Smuzhiyun "kb_row12_ps4"; 485*4882a593Smuzhiyun nvidia,function = "kbc"; 486*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 487*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 488*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 489*4882a593Smuzhiyun }; 490*4882a593Smuzhiyun gen2_i2c_scl_pt5 { 491*4882a593Smuzhiyun nvidia,pins = "gen2_i2c_scl_pt5", 492*4882a593Smuzhiyun "gen2_i2c_sda_pt6"; 493*4882a593Smuzhiyun nvidia,function = "i2c2"; 494*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 495*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 496*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 497*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_ENABLE>; 498*4882a593Smuzhiyun }; 499*4882a593Smuzhiyun sdmmc4_cmd_pt7 { 500*4882a593Smuzhiyun nvidia,pins = "sdmmc4_cmd_pt7", 501*4882a593Smuzhiyun "sdmmc4_dat0_paa0", 502*4882a593Smuzhiyun "sdmmc4_dat1_paa1", 503*4882a593Smuzhiyun "sdmmc4_dat2_paa2", 504*4882a593Smuzhiyun "sdmmc4_dat3_paa3", 505*4882a593Smuzhiyun "sdmmc4_dat4_paa4", 506*4882a593Smuzhiyun "sdmmc4_dat5_paa5", 507*4882a593Smuzhiyun "sdmmc4_dat6_paa6", 508*4882a593Smuzhiyun "sdmmc4_dat7_paa7"; 509*4882a593Smuzhiyun nvidia,function = "sdmmc4"; 510*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 511*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 512*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 513*4882a593Smuzhiyun }; 514*4882a593Smuzhiyun pu0 { 515*4882a593Smuzhiyun nvidia,pins = "pu0", 516*4882a593Smuzhiyun "pu6"; 517*4882a593Smuzhiyun nvidia,function = "rsvd4"; 518*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 519*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 520*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 521*4882a593Smuzhiyun }; 522*4882a593Smuzhiyun jtag_rtck_pu7 { 523*4882a593Smuzhiyun nvidia,pins = "jtag_rtck_pu7"; 524*4882a593Smuzhiyun nvidia,function = "rtck"; 525*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 526*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 527*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 528*4882a593Smuzhiyun }; 529*4882a593Smuzhiyun pv0 { 530*4882a593Smuzhiyun nvidia,pins = "pv0"; 531*4882a593Smuzhiyun nvidia,function = "rsvd1"; 532*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 533*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 534*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 535*4882a593Smuzhiyun }; 536*4882a593Smuzhiyun ddc_scl_pv4 { 537*4882a593Smuzhiyun nvidia,pins = "ddc_scl_pv4", 538*4882a593Smuzhiyun "ddc_sda_pv5"; 539*4882a593Smuzhiyun nvidia,function = "i2c4"; 540*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 541*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 542*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 543*4882a593Smuzhiyun }; 544*4882a593Smuzhiyun crt_hsync_pv6 { 545*4882a593Smuzhiyun nvidia,pins = "crt_hsync_pv6", 546*4882a593Smuzhiyun "crt_vsync_pv7"; 547*4882a593Smuzhiyun nvidia,function = "crt"; 548*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 549*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 550*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 551*4882a593Smuzhiyun }; 552*4882a593Smuzhiyun spi2_cs1_n_pw2 { 553*4882a593Smuzhiyun nvidia,pins = "spi2_cs1_n_pw2", 554*4882a593Smuzhiyun "spi2_miso_px1", 555*4882a593Smuzhiyun "spi2_sck_px2"; 556*4882a593Smuzhiyun nvidia,function = "spi2"; 557*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 558*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 559*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 560*4882a593Smuzhiyun }; 561*4882a593Smuzhiyun clk1_out_pw4 { 562*4882a593Smuzhiyun nvidia,pins = "clk1_out_pw4"; 563*4882a593Smuzhiyun nvidia,function = "extperiph1"; 564*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 565*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 566*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 567*4882a593Smuzhiyun }; 568*4882a593Smuzhiyun clk2_out_pw5 { 569*4882a593Smuzhiyun nvidia,pins = "clk2_out_pw5"; 570*4882a593Smuzhiyun nvidia,function = "extperiph2"; 571*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 572*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 573*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 574*4882a593Smuzhiyun }; 575*4882a593Smuzhiyun spi2_cs0_n_px3 { 576*4882a593Smuzhiyun nvidia,pins = "spi2_cs0_n_px3"; 577*4882a593Smuzhiyun nvidia,function = "spi6"; 578*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 579*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 580*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 581*4882a593Smuzhiyun }; 582*4882a593Smuzhiyun spi1_mosi_px4 { 583*4882a593Smuzhiyun nvidia,pins = "spi1_mosi_px4", 584*4882a593Smuzhiyun "spi1_cs0_n_px6"; 585*4882a593Smuzhiyun nvidia,function = "spi1"; 586*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 587*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 588*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 589*4882a593Smuzhiyun }; 590*4882a593Smuzhiyun ulpi_clk_py0 { 591*4882a593Smuzhiyun nvidia,pins = "ulpi_clk_py0", 592*4882a593Smuzhiyun "ulpi_dir_py1"; 593*4882a593Smuzhiyun nvidia,function = "ulpi"; 594*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 595*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 596*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 597*4882a593Smuzhiyun }; 598*4882a593Smuzhiyun sdmmc1_dat3_py4 { 599*4882a593Smuzhiyun nvidia,pins = "sdmmc1_dat3_py4", 600*4882a593Smuzhiyun "sdmmc1_dat2_py5", 601*4882a593Smuzhiyun "sdmmc1_dat1_py6", 602*4882a593Smuzhiyun "sdmmc1_dat0_py7", 603*4882a593Smuzhiyun "sdmmc1_cmd_pz1"; 604*4882a593Smuzhiyun nvidia,function = "sdmmc1"; 605*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 606*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 607*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun sdmmc1_clk_pz0 { 610*4882a593Smuzhiyun nvidia,pins = "sdmmc1_clk_pz0"; 611*4882a593Smuzhiyun nvidia,function = "sdmmc1"; 612*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 613*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 614*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 615*4882a593Smuzhiyun }; 616*4882a593Smuzhiyun lcd_wr_n_pz3 { 617*4882a593Smuzhiyun nvidia,pins = "lcd_wr_n_pz3"; 618*4882a593Smuzhiyun nvidia,function = "displaya"; 619*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 620*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 621*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 622*4882a593Smuzhiyun }; 623*4882a593Smuzhiyun sys_clk_req_pz5 { 624*4882a593Smuzhiyun nvidia,pins = "sys_clk_req_pz5"; 625*4882a593Smuzhiyun nvidia,function = "sysclk"; 626*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 627*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 628*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 629*4882a593Smuzhiyun }; 630*4882a593Smuzhiyun pwr_i2c_scl_pz6 { 631*4882a593Smuzhiyun nvidia,pins = "pwr_i2c_scl_pz6", 632*4882a593Smuzhiyun "pwr_i2c_sda_pz7"; 633*4882a593Smuzhiyun nvidia,function = "i2cpwr"; 634*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 635*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 636*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 637*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_ENABLE>; 638*4882a593Smuzhiyun }; 639*4882a593Smuzhiyun pbb0 { 640*4882a593Smuzhiyun nvidia,pins = "pbb0", 641*4882a593Smuzhiyun "pcc1"; 642*4882a593Smuzhiyun nvidia,function = "rsvd2"; 643*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 644*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 645*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 646*4882a593Smuzhiyun }; 647*4882a593Smuzhiyun cam_i2c_scl_pbb1 { 648*4882a593Smuzhiyun nvidia,pins = "cam_i2c_scl_pbb1", 649*4882a593Smuzhiyun "cam_i2c_sda_pbb2"; 650*4882a593Smuzhiyun nvidia,function = "i2c3"; 651*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 652*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 653*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 654*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_ENABLE>; 655*4882a593Smuzhiyun }; 656*4882a593Smuzhiyun pbb3 { 657*4882a593Smuzhiyun nvidia,pins = "pbb3"; 658*4882a593Smuzhiyun nvidia,function = "vgp3"; 659*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 660*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 661*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 662*4882a593Smuzhiyun }; 663*4882a593Smuzhiyun pbb4 { 664*4882a593Smuzhiyun nvidia,pins = "pbb4"; 665*4882a593Smuzhiyun nvidia,function = "vgp4"; 666*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 667*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 668*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 669*4882a593Smuzhiyun }; 670*4882a593Smuzhiyun pbb5 { 671*4882a593Smuzhiyun nvidia,pins = "pbb5"; 672*4882a593Smuzhiyun nvidia,function = "vgp5"; 673*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 674*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 675*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 676*4882a593Smuzhiyun }; 677*4882a593Smuzhiyun pbb6 { 678*4882a593Smuzhiyun nvidia,pins = "pbb6"; 679*4882a593Smuzhiyun nvidia,function = "vgp6"; 680*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 681*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 682*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 683*4882a593Smuzhiyun }; 684*4882a593Smuzhiyun pbb7 { 685*4882a593Smuzhiyun nvidia,pins = "pbb7", 686*4882a593Smuzhiyun "pcc2"; 687*4882a593Smuzhiyun nvidia,function = "i2s4"; 688*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 689*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 690*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 691*4882a593Smuzhiyun }; 692*4882a593Smuzhiyun cam_mclk_pcc0 { 693*4882a593Smuzhiyun nvidia,pins = "cam_mclk_pcc0"; 694*4882a593Smuzhiyun nvidia,function = "vi_alt3"; 695*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 696*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 697*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 698*4882a593Smuzhiyun }; 699*4882a593Smuzhiyun sdmmc4_rst_n_pcc3 { 700*4882a593Smuzhiyun nvidia,pins = "sdmmc4_rst_n_pcc3"; 701*4882a593Smuzhiyun nvidia,function = "rsvd2"; 702*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 703*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 704*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 705*4882a593Smuzhiyun }; 706*4882a593Smuzhiyun sdmmc4_clk_pcc4 { 707*4882a593Smuzhiyun nvidia,pins = "sdmmc4_clk_pcc4"; 708*4882a593Smuzhiyun nvidia,function = "sdmmc4"; 709*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 710*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 711*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 712*4882a593Smuzhiyun }; 713*4882a593Smuzhiyun clk2_req_pcc5 { 714*4882a593Smuzhiyun nvidia,pins = "clk2_req_pcc5"; 715*4882a593Smuzhiyun nvidia,function = "dap"; 716*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 717*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 718*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 719*4882a593Smuzhiyun }; 720*4882a593Smuzhiyun pex_l2_rst_n_pcc6 { 721*4882a593Smuzhiyun nvidia,pins = "pex_l2_rst_n_pcc6", 722*4882a593Smuzhiyun "pex_l2_clkreq_n_pcc7"; 723*4882a593Smuzhiyun nvidia,function = "pcie"; 724*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 725*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 726*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 727*4882a593Smuzhiyun }; 728*4882a593Smuzhiyun pex_wake_n_pdd3 { 729*4882a593Smuzhiyun nvidia,pins = "pex_wake_n_pdd3", 730*4882a593Smuzhiyun "pex_l2_prsnt_n_pdd7"; 731*4882a593Smuzhiyun nvidia,function = "pcie"; 732*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 733*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 734*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 735*4882a593Smuzhiyun }; 736*4882a593Smuzhiyun clk3_out_pee0 { 737*4882a593Smuzhiyun nvidia,pins = "clk3_out_pee0"; 738*4882a593Smuzhiyun nvidia,function = "extperiph3"; 739*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 740*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 741*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 742*4882a593Smuzhiyun }; 743*4882a593Smuzhiyun clk1_req_pee2 { 744*4882a593Smuzhiyun nvidia,pins = "clk1_req_pee2"; 745*4882a593Smuzhiyun nvidia,function = "dap"; 746*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 747*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 748*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_DISABLE>; 749*4882a593Smuzhiyun }; 750*4882a593Smuzhiyun hdmi_cec_pee3 { 751*4882a593Smuzhiyun nvidia,pins = "hdmi_cec_pee3"; 752*4882a593Smuzhiyun nvidia,function = "cec"; 753*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 754*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 755*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 756*4882a593Smuzhiyun nvidia,open-drain = <TEGRA_PIN_DISABLE>; 757*4882a593Smuzhiyun }; 758*4882a593Smuzhiyun owr { 759*4882a593Smuzhiyun nvidia,pins = "owr"; 760*4882a593Smuzhiyun nvidia,function = "owr"; 761*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 762*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 763*4882a593Smuzhiyun nvidia,enable-input = <TEGRA_PIN_ENABLE>; 764*4882a593Smuzhiyun }; 765*4882a593Smuzhiyun drive_dap1 { 766*4882a593Smuzhiyun nvidia,pins = "drive_dap1", 767*4882a593Smuzhiyun "drive_dap2", 768*4882a593Smuzhiyun "drive_dbg", 769*4882a593Smuzhiyun "drive_at5", 770*4882a593Smuzhiyun "drive_gme", 771*4882a593Smuzhiyun "drive_ddc", 772*4882a593Smuzhiyun "drive_ao1", 773*4882a593Smuzhiyun "drive_uart3"; 774*4882a593Smuzhiyun nvidia,high-speed-mode = <0>; 775*4882a593Smuzhiyun nvidia,schmitt = <TEGRA_PIN_ENABLE>; 776*4882a593Smuzhiyun nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 777*4882a593Smuzhiyun nvidia,pull-down-strength = <31>; 778*4882a593Smuzhiyun nvidia,pull-up-strength = <31>; 779*4882a593Smuzhiyun nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 780*4882a593Smuzhiyun nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 781*4882a593Smuzhiyun }; 782*4882a593Smuzhiyun drive_sdio1 { 783*4882a593Smuzhiyun nvidia,pins = "drive_sdio1", 784*4882a593Smuzhiyun "drive_sdio3"; 785*4882a593Smuzhiyun nvidia,high-speed-mode = <0>; 786*4882a593Smuzhiyun nvidia,schmitt = <TEGRA_PIN_DISABLE>; 787*4882a593Smuzhiyun nvidia,pull-down-strength = <46>; 788*4882a593Smuzhiyun nvidia,pull-up-strength = <42>; 789*4882a593Smuzhiyun nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; 790*4882a593Smuzhiyun nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; 791*4882a593Smuzhiyun }; 792*4882a593Smuzhiyun drive_gma { 793*4882a593Smuzhiyun nvidia,pins = "drive_gma", 794*4882a593Smuzhiyun "drive_gmb", 795*4882a593Smuzhiyun "drive_gmc", 796*4882a593Smuzhiyun "drive_gmd"; 797*4882a593Smuzhiyun nvidia,pull-down-strength = <9>; 798*4882a593Smuzhiyun nvidia,pull-up-strength = <9>; 799*4882a593Smuzhiyun nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 800*4882a593Smuzhiyun nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 801*4882a593Smuzhiyun }; 802*4882a593Smuzhiyun }; 803*4882a593Smuzhiyun }; 804*4882a593Smuzhiyun 805*4882a593Smuzhiyun uartb: serial@70006040 { 806*4882a593Smuzhiyun compatible = "nvidia,tegra30-hsuart"; 807*4882a593Smuzhiyun /* GPS BCM4751 */ 808*4882a593Smuzhiyun }; 809*4882a593Smuzhiyun 810*4882a593Smuzhiyun uartc: serial@70006200 { 811*4882a593Smuzhiyun compatible = "nvidia,tegra30-hsuart"; 812*4882a593Smuzhiyun status = "okay"; 813*4882a593Smuzhiyun 814*4882a593Smuzhiyun nvidia,adjust-baud-rates = <0 9600 100>, 815*4882a593Smuzhiyun <9600 115200 200>, 816*4882a593Smuzhiyun <1000000 4000000 136>; 817*4882a593Smuzhiyun 818*4882a593Smuzhiyun /* Azurewave AW-NH665 BCM4330B1 */ 819*4882a593Smuzhiyun bluetooth { 820*4882a593Smuzhiyun compatible = "brcm,bcm4330-bt"; 821*4882a593Smuzhiyun 822*4882a593Smuzhiyun max-speed = <4000000>; 823*4882a593Smuzhiyun 824*4882a593Smuzhiyun clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 825*4882a593Smuzhiyun clock-names = "txco"; 826*4882a593Smuzhiyun 827*4882a593Smuzhiyun vbat-supply = <&vdd_3v3_sys>; 828*4882a593Smuzhiyun vddio-supply = <&vdd_1v8>; 829*4882a593Smuzhiyun 830*4882a593Smuzhiyun device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; 831*4882a593Smuzhiyun host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>; 832*4882a593Smuzhiyun shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; 833*4882a593Smuzhiyun }; 834*4882a593Smuzhiyun }; 835*4882a593Smuzhiyun 836*4882a593Smuzhiyun pwm: pwm@7000a000 { 837*4882a593Smuzhiyun status = "okay"; 838*4882a593Smuzhiyun }; 839*4882a593Smuzhiyun 840*4882a593Smuzhiyun i2c@7000c400 { 841*4882a593Smuzhiyun clock-frequency = <400000>; 842*4882a593Smuzhiyun status = "okay"; 843*4882a593Smuzhiyun 844*4882a593Smuzhiyun touchscreen@10 { 845*4882a593Smuzhiyun compatible ="elan,ektf3624"; 846*4882a593Smuzhiyun reg = <0x10>; 847*4882a593Smuzhiyun 848*4882a593Smuzhiyun interrupt-parent = <&gpio>; 849*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_LEVEL_LOW>; 850*4882a593Smuzhiyun 851*4882a593Smuzhiyun reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; 852*4882a593Smuzhiyun 853*4882a593Smuzhiyun vcc33-supply = <&vcc_3v3_ts>; 854*4882a593Smuzhiyun vccio-supply = <&vcc_3v3_ts>; 855*4882a593Smuzhiyun 856*4882a593Smuzhiyun touchscreen-size-x = <2112>; 857*4882a593Smuzhiyun touchscreen-size-y = <1280>; 858*4882a593Smuzhiyun touchscreen-swapped-x-y; 859*4882a593Smuzhiyun touchscreen-inverted-x; 860*4882a593Smuzhiyun }; 861*4882a593Smuzhiyun }; 862*4882a593Smuzhiyun 863*4882a593Smuzhiyun i2c@7000c500 { 864*4882a593Smuzhiyun clock-frequency = <100000>; 865*4882a593Smuzhiyun status = "okay"; 866*4882a593Smuzhiyun 867*4882a593Smuzhiyun compass@e { 868*4882a593Smuzhiyun compatible = "asahi-kasei,ak8974"; 869*4882a593Smuzhiyun reg = <0x0e>; 870*4882a593Smuzhiyun 871*4882a593Smuzhiyun interrupt-parent = <&gpio>; 872*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(W, 0) IRQ_TYPE_EDGE_RISING>; 873*4882a593Smuzhiyun 874*4882a593Smuzhiyun avdd-supply = <&vdd_3v3_sys>; 875*4882a593Smuzhiyun dvdd-supply = <&vdd_1v8>; 876*4882a593Smuzhiyun 877*4882a593Smuzhiyun mount-matrix = "0", "-1", "0", 878*4882a593Smuzhiyun "-1", "0", "0", 879*4882a593Smuzhiyun "0", "0", "-1"; 880*4882a593Smuzhiyun }; 881*4882a593Smuzhiyun 882*4882a593Smuzhiyun light-sensor@1c { 883*4882a593Smuzhiyun compatible = "dynaimage,al3010"; 884*4882a593Smuzhiyun reg = <0x1c>; 885*4882a593Smuzhiyun 886*4882a593Smuzhiyun interrupt-parent = <&gpio>; 887*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; 888*4882a593Smuzhiyun 889*4882a593Smuzhiyun vdd-supply = <&vdd_3v3_sys>; 890*4882a593Smuzhiyun }; 891*4882a593Smuzhiyun 892*4882a593Smuzhiyun accelerometer@68 { 893*4882a593Smuzhiyun compatible = "invensense,mpu6050"; 894*4882a593Smuzhiyun reg = <0x68>; 895*4882a593Smuzhiyun 896*4882a593Smuzhiyun interrupt-parent = <&gpio>; 897*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>; 898*4882a593Smuzhiyun 899*4882a593Smuzhiyun vdd-supply = <&vdd_3v3_sys>; 900*4882a593Smuzhiyun vddio-supply = <&vdd_1v8>; 901*4882a593Smuzhiyun 902*4882a593Smuzhiyun mount-matrix = "0", "-1", "0", 903*4882a593Smuzhiyun "-1", "0", "0", 904*4882a593Smuzhiyun "0", "0", "-1"; 905*4882a593Smuzhiyun }; 906*4882a593Smuzhiyun }; 907*4882a593Smuzhiyun 908*4882a593Smuzhiyun i2c@7000d000 { 909*4882a593Smuzhiyun clock-frequency = <100000>; 910*4882a593Smuzhiyun status = "okay"; 911*4882a593Smuzhiyun 912*4882a593Smuzhiyun rt5640: audio-codec@1c { 913*4882a593Smuzhiyun compatible = "realtek,rt5640"; 914*4882a593Smuzhiyun reg = <0x1c>; 915*4882a593Smuzhiyun 916*4882a593Smuzhiyun realtek,dmic1-data-pin = <1>; 917*4882a593Smuzhiyun }; 918*4882a593Smuzhiyun 919*4882a593Smuzhiyun nct72: temperature-sensor@4c { 920*4882a593Smuzhiyun compatible = "onnn,nct1008"; 921*4882a593Smuzhiyun reg = <0x4c>; 922*4882a593Smuzhiyun vcc-supply = <&vdd_3v3_sys>; 923*4882a593Smuzhiyun #thermal-sensor-cells = <1>; 924*4882a593Smuzhiyun }; 925*4882a593Smuzhiyun 926*4882a593Smuzhiyun fuel-gauge@55 { 927*4882a593Smuzhiyun compatible = "ti,bq27541"; 928*4882a593Smuzhiyun reg = <0x55>; 929*4882a593Smuzhiyun power-supplies = <&power_supply>; 930*4882a593Smuzhiyun monitored-battery = <&battery_cell>; 931*4882a593Smuzhiyun }; 932*4882a593Smuzhiyun 933*4882a593Smuzhiyun power_supply: charger@6a { 934*4882a593Smuzhiyun compatible = "summit,smb347"; 935*4882a593Smuzhiyun reg = <0x6a>; 936*4882a593Smuzhiyun 937*4882a593Smuzhiyun interrupt-parent = <&gpio>; 938*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(V, 1) IRQ_TYPE_EDGE_BOTH>; 939*4882a593Smuzhiyun 940*4882a593Smuzhiyun summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW>; 941*4882a593Smuzhiyun summit,enable-usb-charging; 942*4882a593Smuzhiyun 943*4882a593Smuzhiyun monitored-battery = <&battery_cell>; 944*4882a593Smuzhiyun }; 945*4882a593Smuzhiyun }; 946*4882a593Smuzhiyun 947*4882a593Smuzhiyun pmc@7000e400 { 948*4882a593Smuzhiyun status = "okay"; 949*4882a593Smuzhiyun nvidia,invert-interrupt; 950*4882a593Smuzhiyun nvidia,suspend-mode = <1>; 951*4882a593Smuzhiyun nvidia,cpu-pwr-good-time = <2000>; 952*4882a593Smuzhiyun nvidia,cpu-pwr-off-time = <200>; 953*4882a593Smuzhiyun nvidia,core-pwr-good-time = <3845 3845>; 954*4882a593Smuzhiyun nvidia,core-pwr-off-time = <0>; 955*4882a593Smuzhiyun nvidia,core-power-req-active-high; 956*4882a593Smuzhiyun nvidia,sys-clock-req-active-high; 957*4882a593Smuzhiyun }; 958*4882a593Smuzhiyun 959*4882a593Smuzhiyun ahub@70080000 { 960*4882a593Smuzhiyun i2s@70080400 { 961*4882a593Smuzhiyun status = "okay"; 962*4882a593Smuzhiyun }; 963*4882a593Smuzhiyun }; 964*4882a593Smuzhiyun 965*4882a593Smuzhiyun brcm_wifi_pwrseq: wifi-pwrseq { 966*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 967*4882a593Smuzhiyun 968*4882a593Smuzhiyun clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 969*4882a593Smuzhiyun clock-names = "ext_clock"; 970*4882a593Smuzhiyun 971*4882a593Smuzhiyun reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; 972*4882a593Smuzhiyun post-power-on-delay-ms = <300>; 973*4882a593Smuzhiyun power-off-delay-us = <300>; 974*4882a593Smuzhiyun }; 975*4882a593Smuzhiyun 976*4882a593Smuzhiyun sdmmc3: mmc@78000400 { 977*4882a593Smuzhiyun status = "okay"; 978*4882a593Smuzhiyun 979*4882a593Smuzhiyun #address-cells = <1>; 980*4882a593Smuzhiyun #size-cells = <0>; 981*4882a593Smuzhiyun 982*4882a593Smuzhiyun assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 983*4882a593Smuzhiyun assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; 984*4882a593Smuzhiyun assigned-clock-rates = <50000000>; 985*4882a593Smuzhiyun 986*4882a593Smuzhiyun max-frequency = <50000000>; 987*4882a593Smuzhiyun keep-power-in-suspend; 988*4882a593Smuzhiyun bus-width = <4>; 989*4882a593Smuzhiyun non-removable; 990*4882a593Smuzhiyun 991*4882a593Smuzhiyun mmc-pwrseq = <&brcm_wifi_pwrseq>; 992*4882a593Smuzhiyun vmmc-supply = <&vdd_3v3_sys>; 993*4882a593Smuzhiyun vqmmc-supply = <&vdd_1v8>; 994*4882a593Smuzhiyun 995*4882a593Smuzhiyun /* Azurewave AW-NH665 BCM4330 */ 996*4882a593Smuzhiyun wifi@1 { 997*4882a593Smuzhiyun reg = <1>; 998*4882a593Smuzhiyun compatible = "brcm,bcm4329-fmac"; 999*4882a593Smuzhiyun interrupt-parent = <&gpio>; 1000*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>; 1001*4882a593Smuzhiyun interrupt-names = "host-wake"; 1002*4882a593Smuzhiyun }; 1003*4882a593Smuzhiyun }; 1004*4882a593Smuzhiyun 1005*4882a593Smuzhiyun sdmmc4: mmc@78000600 { 1006*4882a593Smuzhiyun status = "okay"; 1007*4882a593Smuzhiyun bus-width = <8>; 1008*4882a593Smuzhiyun vmmc-supply = <&vcore_emmc>; 1009*4882a593Smuzhiyun vqmmc-supply = <&vdd_1v8>; 1010*4882a593Smuzhiyun non-removable; 1011*4882a593Smuzhiyun }; 1012*4882a593Smuzhiyun 1013*4882a593Smuzhiyun usb@7d000000 { 1014*4882a593Smuzhiyun compatible = "nvidia,tegra30-udc"; 1015*4882a593Smuzhiyun status = "okay"; 1016*4882a593Smuzhiyun dr_mode = "peripheral"; 1017*4882a593Smuzhiyun }; 1018*4882a593Smuzhiyun 1019*4882a593Smuzhiyun usb-phy@7d000000 { 1020*4882a593Smuzhiyun status = "okay"; 1021*4882a593Smuzhiyun dr_mode = "peripheral"; 1022*4882a593Smuzhiyun nvidia,hssync-start-delay = <0>; 1023*4882a593Smuzhiyun nvidia,xcvr-lsfslew = <2>; 1024*4882a593Smuzhiyun nvidia,xcvr-lsrslew = <2>; 1025*4882a593Smuzhiyun }; 1026*4882a593Smuzhiyun 1027*4882a593Smuzhiyun backlight: backlight { 1028*4882a593Smuzhiyun compatible = "pwm-backlight"; 1029*4882a593Smuzhiyun 1030*4882a593Smuzhiyun power-supply = <&vdd_5v0_sys>; 1031*4882a593Smuzhiyun pwms = <&pwm 0 50000>; 1032*4882a593Smuzhiyun 1033*4882a593Smuzhiyun brightness-levels = <1 255>; 1034*4882a593Smuzhiyun num-interpolated-steps = <254>; 1035*4882a593Smuzhiyun default-brightness-level = <15>; 1036*4882a593Smuzhiyun }; 1037*4882a593Smuzhiyun 1038*4882a593Smuzhiyun battery_cell: battery-cell { 1039*4882a593Smuzhiyun compatible = "simple-battery"; 1040*4882a593Smuzhiyun constant-charge-current-max-microamp = <1800000>; 1041*4882a593Smuzhiyun operating-range-celsius = <0 45>; 1042*4882a593Smuzhiyun }; 1043*4882a593Smuzhiyun 1044*4882a593Smuzhiyun /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 1045*4882a593Smuzhiyun clk32k_in: clock@0 { 1046*4882a593Smuzhiyun compatible = "fixed-clock"; 1047*4882a593Smuzhiyun #clock-cells = <0>; 1048*4882a593Smuzhiyun clock-frequency = <32768>; 1049*4882a593Smuzhiyun clock-output-names = "pmic-oscillator"; 1050*4882a593Smuzhiyun }; 1051*4882a593Smuzhiyun 1052*4882a593Smuzhiyun cpus { 1053*4882a593Smuzhiyun cpu0: cpu@0 { 1054*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 1055*4882a593Smuzhiyun operating-points-v2 = <&cpu0_opp_table>; 1056*4882a593Smuzhiyun #cooling-cells = <2>; 1057*4882a593Smuzhiyun }; 1058*4882a593Smuzhiyun 1059*4882a593Smuzhiyun cpu@1 { 1060*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 1061*4882a593Smuzhiyun operating-points-v2 = <&cpu0_opp_table>; 1062*4882a593Smuzhiyun }; 1063*4882a593Smuzhiyun 1064*4882a593Smuzhiyun cpu@2 { 1065*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 1066*4882a593Smuzhiyun operating-points-v2 = <&cpu0_opp_table>; 1067*4882a593Smuzhiyun }; 1068*4882a593Smuzhiyun 1069*4882a593Smuzhiyun cpu@3 { 1070*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 1071*4882a593Smuzhiyun operating-points-v2 = <&cpu0_opp_table>; 1072*4882a593Smuzhiyun }; 1073*4882a593Smuzhiyun }; 1074*4882a593Smuzhiyun 1075*4882a593Smuzhiyun display-panel { 1076*4882a593Smuzhiyun compatible = "hydis,hv070wx2-1e0", "chunghwa,claa070wp03xg", 1077*4882a593Smuzhiyun "panel-lvds"; 1078*4882a593Smuzhiyun 1079*4882a593Smuzhiyun power-supply = <&vdd_pnl>; 1080*4882a593Smuzhiyun backlight = <&backlight>; 1081*4882a593Smuzhiyun 1082*4882a593Smuzhiyun width-mm = <94>; 1083*4882a593Smuzhiyun height-mm = <150>; 1084*4882a593Smuzhiyun rotation = <180>; 1085*4882a593Smuzhiyun 1086*4882a593Smuzhiyun data-mapping = "jeida-24"; 1087*4882a593Smuzhiyun 1088*4882a593Smuzhiyun port { 1089*4882a593Smuzhiyun panel_input: endpoint { 1090*4882a593Smuzhiyun remote-endpoint = <&lvds_encoder_output>; 1091*4882a593Smuzhiyun }; 1092*4882a593Smuzhiyun }; 1093*4882a593Smuzhiyun }; 1094*4882a593Smuzhiyun 1095*4882a593Smuzhiyun firmware { 1096*4882a593Smuzhiyun trusted-foundations { 1097*4882a593Smuzhiyun compatible = "tlm,trusted-foundations"; 1098*4882a593Smuzhiyun tlm,version-major = <0x0>; 1099*4882a593Smuzhiyun tlm,version-minor = <0x0>; 1100*4882a593Smuzhiyun }; 1101*4882a593Smuzhiyun }; 1102*4882a593Smuzhiyun 1103*4882a593Smuzhiyun gpio-keys { 1104*4882a593Smuzhiyun compatible = "gpio-keys"; 1105*4882a593Smuzhiyun 1106*4882a593Smuzhiyun hall-sensor { 1107*4882a593Smuzhiyun label = "Lid"; 1108*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; 1109*4882a593Smuzhiyun linux,input-type = <EV_SW>; 1110*4882a593Smuzhiyun linux,code = <SW_LID>; 1111*4882a593Smuzhiyun debounce-interval = <500>; 1112*4882a593Smuzhiyun wakeup-event-action = <EV_ACT_DEASSERTED>; 1113*4882a593Smuzhiyun wakeup-source; 1114*4882a593Smuzhiyun }; 1115*4882a593Smuzhiyun 1116*4882a593Smuzhiyun power { 1117*4882a593Smuzhiyun label = "Power"; 1118*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; 1119*4882a593Smuzhiyun linux,code = <KEY_POWER>; 1120*4882a593Smuzhiyun debounce-interval = <10>; 1121*4882a593Smuzhiyun wakeup-event-action = <EV_ACT_ASSERTED>; 1122*4882a593Smuzhiyun wakeup-source; 1123*4882a593Smuzhiyun }; 1124*4882a593Smuzhiyun 1125*4882a593Smuzhiyun volume-up { 1126*4882a593Smuzhiyun label = "Volume Up"; 1127*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; 1128*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 1129*4882a593Smuzhiyun debounce-interval = <10>; 1130*4882a593Smuzhiyun wakeup-event-action = <EV_ACT_ASSERTED>; 1131*4882a593Smuzhiyun wakeup-source; 1132*4882a593Smuzhiyun }; 1133*4882a593Smuzhiyun 1134*4882a593Smuzhiyun volume-down { 1135*4882a593Smuzhiyun label = "Volume Down"; 1136*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; 1137*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 1138*4882a593Smuzhiyun debounce-interval = <10>; 1139*4882a593Smuzhiyun wakeup-event-action = <EV_ACT_ASSERTED>; 1140*4882a593Smuzhiyun wakeup-source; 1141*4882a593Smuzhiyun }; 1142*4882a593Smuzhiyun }; 1143*4882a593Smuzhiyun 1144*4882a593Smuzhiyun lvds-encoder { 1145*4882a593Smuzhiyun compatible = "ti,sn75lvds83", "lvds-encoder"; 1146*4882a593Smuzhiyun 1147*4882a593Smuzhiyun powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; 1148*4882a593Smuzhiyun 1149*4882a593Smuzhiyun ports { 1150*4882a593Smuzhiyun #address-cells = <1>; 1151*4882a593Smuzhiyun #size-cells = <0>; 1152*4882a593Smuzhiyun 1153*4882a593Smuzhiyun port@0 { 1154*4882a593Smuzhiyun reg = <0>; 1155*4882a593Smuzhiyun 1156*4882a593Smuzhiyun lvds_encoder_input: endpoint { 1157*4882a593Smuzhiyun remote-endpoint = <&lcd_output>; 1158*4882a593Smuzhiyun }; 1159*4882a593Smuzhiyun }; 1160*4882a593Smuzhiyun 1161*4882a593Smuzhiyun port@1 { 1162*4882a593Smuzhiyun reg = <1>; 1163*4882a593Smuzhiyun 1164*4882a593Smuzhiyun lvds_encoder_output: endpoint { 1165*4882a593Smuzhiyun remote-endpoint = <&panel_input>; 1166*4882a593Smuzhiyun }; 1167*4882a593Smuzhiyun }; 1168*4882a593Smuzhiyun }; 1169*4882a593Smuzhiyun }; 1170*4882a593Smuzhiyun 1171*4882a593Smuzhiyun vdd_5v0_sys: regulator@0 { 1172*4882a593Smuzhiyun compatible = "regulator-fixed"; 1173*4882a593Smuzhiyun regulator-name = "vdd_5v0"; 1174*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 1175*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 1176*4882a593Smuzhiyun regulator-always-on; 1177*4882a593Smuzhiyun regulator-boot-on; 1178*4882a593Smuzhiyun }; 1179*4882a593Smuzhiyun 1180*4882a593Smuzhiyun vdd_3v3_sys: regulator@1 { 1181*4882a593Smuzhiyun compatible = "regulator-fixed"; 1182*4882a593Smuzhiyun regulator-name = "vdd_3v3"; 1183*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 1184*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 1185*4882a593Smuzhiyun regulator-always-on; 1186*4882a593Smuzhiyun regulator-boot-on; 1187*4882a593Smuzhiyun vin-supply = <&vdd_5v0_sys>; 1188*4882a593Smuzhiyun }; 1189*4882a593Smuzhiyun 1190*4882a593Smuzhiyun vdd_pnl: regulator@2 { 1191*4882a593Smuzhiyun compatible = "regulator-fixed"; 1192*4882a593Smuzhiyun regulator-name = "vdd_panel"; 1193*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 1194*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 1195*4882a593Smuzhiyun regulator-enable-ramp-delay = <300000>; 1196*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; 1197*4882a593Smuzhiyun enable-active-high; 1198*4882a593Smuzhiyun vin-supply = <&vdd_3v3_sys>; 1199*4882a593Smuzhiyun }; 1200*4882a593Smuzhiyun 1201*4882a593Smuzhiyun vcc_3v3_ts: regulator@3 { 1202*4882a593Smuzhiyun compatible = "regulator-fixed"; 1203*4882a593Smuzhiyun regulator-name = "ldo_s-1167_3v3"; 1204*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 1205*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 1206*4882a593Smuzhiyun regulator-always-on; 1207*4882a593Smuzhiyun regulator-boot-on; 1208*4882a593Smuzhiyun vin-supply = <&vdd_5v0_sys>; 1209*4882a593Smuzhiyun }; 1210*4882a593Smuzhiyun 1211*4882a593Smuzhiyun sound { 1212*4882a593Smuzhiyun compatible = "nvidia,tegra-audio-rt5640-grouper", 1213*4882a593Smuzhiyun "nvidia,tegra-audio-rt5640"; 1214*4882a593Smuzhiyun nvidia,model = "ASUS Google Nexus 7 ALC5642"; 1215*4882a593Smuzhiyun 1216*4882a593Smuzhiyun nvidia,audio-routing = 1217*4882a593Smuzhiyun "Headphones", "HPOR", 1218*4882a593Smuzhiyun "Headphones", "HPOL", 1219*4882a593Smuzhiyun "Speakers", "SPORP", 1220*4882a593Smuzhiyun "Speakers", "SPORN", 1221*4882a593Smuzhiyun "Speakers", "SPOLP", 1222*4882a593Smuzhiyun "Speakers", "SPOLN", 1223*4882a593Smuzhiyun "DMIC1", "Mic Jack"; 1224*4882a593Smuzhiyun 1225*4882a593Smuzhiyun nvidia,i2s-controller = <&tegra_i2s1>; 1226*4882a593Smuzhiyun nvidia,audio-codec = <&rt5640>; 1227*4882a593Smuzhiyun 1228*4882a593Smuzhiyun nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; 1229*4882a593Smuzhiyun 1230*4882a593Smuzhiyun clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 1231*4882a593Smuzhiyun <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1232*4882a593Smuzhiyun <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1233*4882a593Smuzhiyun clock-names = "pll_a", "pll_a_out0", "mclk"; 1234*4882a593Smuzhiyun 1235*4882a593Smuzhiyun assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, 1236*4882a593Smuzhiyun <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1237*4882a593Smuzhiyun 1238*4882a593Smuzhiyun assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1239*4882a593Smuzhiyun <&tegra_car TEGRA30_CLK_EXTERN1>; 1240*4882a593Smuzhiyun }; 1241*4882a593Smuzhiyun 1242*4882a593Smuzhiyun thermal-zones { 1243*4882a593Smuzhiyun nct72-local { 1244*4882a593Smuzhiyun polling-delay-passive = <1000>; /* milliseconds */ 1245*4882a593Smuzhiyun polling-delay = <0>; /* milliseconds */ 1246*4882a593Smuzhiyun 1247*4882a593Smuzhiyun thermal-sensors = <&nct72 0>; 1248*4882a593Smuzhiyun }; 1249*4882a593Smuzhiyun 1250*4882a593Smuzhiyun nct72-remote { 1251*4882a593Smuzhiyun polling-delay-passive = <1000>; /* milliseconds */ 1252*4882a593Smuzhiyun polling-delay = <5000>; /* milliseconds */ 1253*4882a593Smuzhiyun 1254*4882a593Smuzhiyun thermal-sensors = <&nct72 1>; 1255*4882a593Smuzhiyun 1256*4882a593Smuzhiyun trips { 1257*4882a593Smuzhiyun trip0: cpu-alert0 { 1258*4882a593Smuzhiyun /* start throttling at 50C */ 1259*4882a593Smuzhiyun temperature = <50000>; 1260*4882a593Smuzhiyun hysteresis = <3000>; 1261*4882a593Smuzhiyun type = "passive"; 1262*4882a593Smuzhiyun }; 1263*4882a593Smuzhiyun 1264*4882a593Smuzhiyun trip1: cpu-crit { 1265*4882a593Smuzhiyun /* shut down at 60C */ 1266*4882a593Smuzhiyun temperature = <60000>; 1267*4882a593Smuzhiyun hysteresis = <2000>; 1268*4882a593Smuzhiyun type = "critical"; 1269*4882a593Smuzhiyun }; 1270*4882a593Smuzhiyun }; 1271*4882a593Smuzhiyun 1272*4882a593Smuzhiyun cooling-maps { 1273*4882a593Smuzhiyun map0 { 1274*4882a593Smuzhiyun trip = <&trip0>; 1275*4882a593Smuzhiyun cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1276*4882a593Smuzhiyun }; 1277*4882a593Smuzhiyun }; 1278*4882a593Smuzhiyun }; 1279*4882a593Smuzhiyun }; 1280*4882a593Smuzhiyun}; 1281