xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 OR MIT
2*4882a593Smuzhiyun/dts-v1/;
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
5*4882a593Smuzhiyun#include "tegra30-apalis-v1.1.dtsi"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/ {
8*4882a593Smuzhiyun	model = "Toradex Apalis T30 on Apalis Evaluation Board";
9*4882a593Smuzhiyun	compatible = "toradex,apalis_t30-v1.1-eval", "toradex,apalis_t30-eval",
10*4882a593Smuzhiyun		     "toradex,apalis_t30-v1.1", "toradex,apalis_t30",
11*4882a593Smuzhiyun		     "nvidia,tegra30";
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	aliases {
14*4882a593Smuzhiyun		rtc0 = "/i2c@7000c000/rtc@68";
15*4882a593Smuzhiyun		rtc1 = "/i2c@7000d000/pmic@2d";
16*4882a593Smuzhiyun		rtc2 = "/rtc@7000e000";
17*4882a593Smuzhiyun		serial0 = &uarta;
18*4882a593Smuzhiyun		serial1 = &uartb;
19*4882a593Smuzhiyun		serial2 = &uartc;
20*4882a593Smuzhiyun		serial3 = &uartd;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	chosen {
24*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	pcie@3000 {
28*4882a593Smuzhiyun		pci@1,0 {
29*4882a593Smuzhiyun			status = "okay";
30*4882a593Smuzhiyun		};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun		pci@2,0 {
33*4882a593Smuzhiyun			status = "okay";
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	host1x@50000000 {
38*4882a593Smuzhiyun		dc@54200000 {
39*4882a593Smuzhiyun			rgb {
40*4882a593Smuzhiyun				status = "okay";
41*4882a593Smuzhiyun				nvidia,panel = <&panel>;
42*4882a593Smuzhiyun			};
43*4882a593Smuzhiyun		};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun		hdmi@54280000 {
46*4882a593Smuzhiyun			status = "okay";
47*4882a593Smuzhiyun			hdmi-supply = <&reg_5v0>;
48*4882a593Smuzhiyun		};
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	/* Apalis UART1 */
52*4882a593Smuzhiyun	serial@70006000 {
53*4882a593Smuzhiyun		status = "okay";
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	/* Apalis UART2 */
57*4882a593Smuzhiyun	serial@70006040 {
58*4882a593Smuzhiyun		status = "okay";
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun	/* Apalis UART3 */
62*4882a593Smuzhiyun	serial@70006200 {
63*4882a593Smuzhiyun		status = "okay";
64*4882a593Smuzhiyun	};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun	/* Apalis UART4 */
67*4882a593Smuzhiyun	serial@70006300 {
68*4882a593Smuzhiyun		status = "okay";
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	pwm@7000a000 {
72*4882a593Smuzhiyun		status = "okay";
73*4882a593Smuzhiyun	};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun	/*
76*4882a593Smuzhiyun	 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
77*4882a593Smuzhiyun	 * board)
78*4882a593Smuzhiyun	 */
79*4882a593Smuzhiyun	i2c@7000c000 {
80*4882a593Smuzhiyun		status = "okay";
81*4882a593Smuzhiyun		clock-frequency = <400000>;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun		pcie-switch@58 {
84*4882a593Smuzhiyun			compatible = "plx,pex8605";
85*4882a593Smuzhiyun			reg = <0x58>;
86*4882a593Smuzhiyun		};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun		/* M41T0M6 real time clock on carrier board */
89*4882a593Smuzhiyun		rtc@68 {
90*4882a593Smuzhiyun			compatible = "st,m41t0";
91*4882a593Smuzhiyun			reg = <0x68>;
92*4882a593Smuzhiyun		};
93*4882a593Smuzhiyun	};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun	/* GEN2_I2C: unused */
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun	/*
98*4882a593Smuzhiyun	 * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
99*4882a593Smuzhiyun	 * carrier board)
100*4882a593Smuzhiyun	 */
101*4882a593Smuzhiyun	i2c@7000c500 {
102*4882a593Smuzhiyun		status = "okay";
103*4882a593Smuzhiyun		clock-frequency = <400000>;
104*4882a593Smuzhiyun	};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun	/* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
107*4882a593Smuzhiyun	i2c@7000c700 {
108*4882a593Smuzhiyun		status = "okay";
109*4882a593Smuzhiyun	};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun	/* SPI1: Apalis SPI1 */
112*4882a593Smuzhiyun	spi@7000d400 {
113*4882a593Smuzhiyun		status = "okay";
114*4882a593Smuzhiyun		spi-max-frequency = <25000000>;
115*4882a593Smuzhiyun	};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun	/* SPI5: Apalis SPI2 */
118*4882a593Smuzhiyun	spi@7000dc00 {
119*4882a593Smuzhiyun		status = "okay";
120*4882a593Smuzhiyun		spi-max-frequency = <25000000>;
121*4882a593Smuzhiyun	};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun	/* Apalis SD1 */
124*4882a593Smuzhiyun	mmc@78000000 {
125*4882a593Smuzhiyun		status = "okay";
126*4882a593Smuzhiyun		bus-width = <4>;
127*4882a593Smuzhiyun		/* SD1_CD# */
128*4882a593Smuzhiyun		cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
129*4882a593Smuzhiyun		no-1-8-v;
130*4882a593Smuzhiyun	};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun	/* Apalis MMC1 */
133*4882a593Smuzhiyun	mmc@78000400 {
134*4882a593Smuzhiyun		status = "okay";
135*4882a593Smuzhiyun		bus-width = <8>;
136*4882a593Smuzhiyun		/* MMC1_CD# */
137*4882a593Smuzhiyun		cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
138*4882a593Smuzhiyun		vqmmc-supply = <&reg_vddio_sdmmc3>;
139*4882a593Smuzhiyun	};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun	/* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
142*4882a593Smuzhiyun	usb@7d000000 {
143*4882a593Smuzhiyun		status = "okay";
144*4882a593Smuzhiyun		dr_mode = "otg";
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun	usb-phy@7d000000 {
148*4882a593Smuzhiyun		status = "okay";
149*4882a593Smuzhiyun		vbus-supply = <&reg_usbo1_vbus>;
150*4882a593Smuzhiyun	};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun	/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
153*4882a593Smuzhiyun	usb@7d004000 {
154*4882a593Smuzhiyun		status = "okay";
155*4882a593Smuzhiyun	};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun	usb-phy@7d004000 {
158*4882a593Smuzhiyun		status = "okay";
159*4882a593Smuzhiyun		vbus-supply = <&reg_usbh_vbus>;
160*4882a593Smuzhiyun	};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun	/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
163*4882a593Smuzhiyun	usb@7d008000 {
164*4882a593Smuzhiyun		status = "okay";
165*4882a593Smuzhiyun	};
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun	usb-phy@7d008000 {
168*4882a593Smuzhiyun		status = "okay";
169*4882a593Smuzhiyun		vbus-supply = <&reg_usbh_vbus>;
170*4882a593Smuzhiyun	};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun	backlight: backlight {
173*4882a593Smuzhiyun		compatible = "pwm-backlight";
174*4882a593Smuzhiyun		brightness-levels = <255 231 223 207 191 159 127 0>;
175*4882a593Smuzhiyun		default-brightness-level = <6>;
176*4882a593Smuzhiyun		/* BKL1_ON */
177*4882a593Smuzhiyun		enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
178*4882a593Smuzhiyun		power-supply = <&reg_3v3>;
179*4882a593Smuzhiyun		pwms = <&pwm 0 5000000>; /* BKL1_PWM */
180*4882a593Smuzhiyun	};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun	gpio-keys {
183*4882a593Smuzhiyun		compatible = "gpio-keys";
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun		wakeup {
186*4882a593Smuzhiyun			label = "WAKE1_MICO";
187*4882a593Smuzhiyun			gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
188*4882a593Smuzhiyun			linux,code = <KEY_WAKEUP>;
189*4882a593Smuzhiyun			debounce-interval = <10>;
190*4882a593Smuzhiyun			wakeup-source;
191*4882a593Smuzhiyun		};
192*4882a593Smuzhiyun	};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun	panel: panel {
195*4882a593Smuzhiyun		/*
196*4882a593Smuzhiyun		 * edt,et057090dhu: EDT 5.7" LCD TFT
197*4882a593Smuzhiyun		 * edt,et070080dh6: EDT 7.0" LCD TFT
198*4882a593Smuzhiyun		 */
199*4882a593Smuzhiyun		compatible = "edt,et057090dhu";
200*4882a593Smuzhiyun		backlight = <&backlight>;
201*4882a593Smuzhiyun		power-supply = <&reg_3v3>;
202*4882a593Smuzhiyun	};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun	reg_3v3: regulator-3v3 {
205*4882a593Smuzhiyun		compatible = "regulator-fixed";
206*4882a593Smuzhiyun		regulator-name = "3.3V_SW";
207*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
208*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
209*4882a593Smuzhiyun	};
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun	reg_5v0: regulator-5v0 {
212*4882a593Smuzhiyun		compatible = "regulator-fixed";
213*4882a593Smuzhiyun		regulator-name = "5V_SW";
214*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
215*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
216*4882a593Smuzhiyun	};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun	/* USBO1_EN */
219*4882a593Smuzhiyun	reg_usbo1_vbus: regulator-usbo1-vbus {
220*4882a593Smuzhiyun		compatible = "regulator-fixed";
221*4882a593Smuzhiyun		regulator-name = "VCC_USBO1";
222*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
223*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
224*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
225*4882a593Smuzhiyun		enable-active-high;
226*4882a593Smuzhiyun		vin-supply = <&reg_5v0>;
227*4882a593Smuzhiyun	};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun	/* USBH_EN */
230*4882a593Smuzhiyun	reg_usbh_vbus: regulator-usbh-vbus {
231*4882a593Smuzhiyun		compatible = "regulator-fixed";
232*4882a593Smuzhiyun		regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
233*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
234*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
235*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
236*4882a593Smuzhiyun		enable-active-high;
237*4882a593Smuzhiyun		vin-supply = <&reg_5v0>;
238*4882a593Smuzhiyun	};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun	/*
241*4882a593Smuzhiyun	 * 1.8 volt resp. 3.3 volt VDDIO_SDMMC3 depending on
242*4882a593Smuzhiyun	 * EN_+3.3_SDMMC3 GPIO
243*4882a593Smuzhiyun	 */
244*4882a593Smuzhiyun	reg_vddio_sdmmc3: regulator-vddio-sdmmc3 {
245*4882a593Smuzhiyun		compatible = "regulator-gpio";
246*4882a593Smuzhiyun		regulator-name = "VDDIO_SDMMC3";
247*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
248*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
249*4882a593Smuzhiyun		regulator-type = "voltage";
250*4882a593Smuzhiyun		gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>;
251*4882a593Smuzhiyun		states = <1800000 0x0>,
252*4882a593Smuzhiyun			 <3300000 0x1>;
253*4882a593Smuzhiyun		startup-delay-us = <100000>;
254*4882a593Smuzhiyun		vin-supply = <&vddio_sdmmc_1v8_reg>;
255*4882a593Smuzhiyun	};
256*4882a593Smuzhiyun};
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun&gpio {
259*4882a593Smuzhiyun	/* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
260*4882a593Smuzhiyun	pex-perst-n {
261*4882a593Smuzhiyun		gpio-hog;
262*4882a593Smuzhiyun		gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
263*4882a593Smuzhiyun		output-high;
264*4882a593Smuzhiyun		line-name = "PEX_PERST_N";
265*4882a593Smuzhiyun	};
266*4882a593Smuzhiyun};
267