1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 5*4882a593Smuzhiyun#include "tegra30-apalis.dtsi" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun model = "Toradex Apalis T30 on Apalis Evaluation Board"; 9*4882a593Smuzhiyun compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30", 10*4882a593Smuzhiyun "nvidia,tegra30"; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun aliases { 13*4882a593Smuzhiyun rtc0 = "/i2c@7000c000/rtc@68"; 14*4882a593Smuzhiyun rtc1 = "/i2c@7000d000/pmic@2d"; 15*4882a593Smuzhiyun rtc2 = "/rtc@7000e000"; 16*4882a593Smuzhiyun serial0 = &uarta; 17*4882a593Smuzhiyun serial1 = &uartb; 18*4882a593Smuzhiyun serial2 = &uartc; 19*4882a593Smuzhiyun serial3 = &uartd; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun chosen { 23*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun pcie@3000 { 27*4882a593Smuzhiyun pci@1,0 { 28*4882a593Smuzhiyun status = "okay"; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun pci@2,0 { 32*4882a593Smuzhiyun status = "okay"; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun host1x@50000000 { 37*4882a593Smuzhiyun dc@54200000 { 38*4882a593Smuzhiyun rgb { 39*4882a593Smuzhiyun status = "okay"; 40*4882a593Smuzhiyun nvidia,panel = <&panel>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun hdmi@54280000 { 45*4882a593Smuzhiyun status = "okay"; 46*4882a593Smuzhiyun hdmi-supply = <®_5v0>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Apalis UART1 */ 51*4882a593Smuzhiyun serial@70006000 { 52*4882a593Smuzhiyun status = "okay"; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Apalis UART2 */ 56*4882a593Smuzhiyun serial@70006040 { 57*4882a593Smuzhiyun status = "okay"; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Apalis UART3 */ 61*4882a593Smuzhiyun serial@70006200 { 62*4882a593Smuzhiyun status = "okay"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Apalis UART4 */ 66*4882a593Smuzhiyun serial@70006300 { 67*4882a593Smuzhiyun status = "okay"; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun pwm@7000a000 { 71*4882a593Smuzhiyun status = "okay"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier 76*4882a593Smuzhiyun * board) 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun i2c@7000c000 { 79*4882a593Smuzhiyun status = "okay"; 80*4882a593Smuzhiyun clock-frequency = <400000>; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun pcie-switch@58 { 83*4882a593Smuzhiyun compatible = "plx,pex8605"; 84*4882a593Smuzhiyun reg = <0x58>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* M41T0M6 real time clock on carrier board */ 88*4882a593Smuzhiyun rtc@68 { 89*4882a593Smuzhiyun compatible = "st,m41t0"; 90*4882a593Smuzhiyun reg = <0x68>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* GEN2_I2C: unused */ 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on 98*4882a593Smuzhiyun * carrier board) 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun i2c@7000c500 { 101*4882a593Smuzhiyun status = "okay"; 102*4882a593Smuzhiyun clock-frequency = <400000>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ 106*4882a593Smuzhiyun i2c@7000c700 { 107*4882a593Smuzhiyun status = "okay"; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* SPI1: Apalis SPI1 */ 111*4882a593Smuzhiyun spi@7000d400 { 112*4882a593Smuzhiyun status = "okay"; 113*4882a593Smuzhiyun spi-max-frequency = <25000000>; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* SPI5: Apalis SPI2 */ 117*4882a593Smuzhiyun spi@7000dc00 { 118*4882a593Smuzhiyun status = "okay"; 119*4882a593Smuzhiyun spi-max-frequency = <25000000>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* Apalis SD1 */ 123*4882a593Smuzhiyun mmc@78000000 { 124*4882a593Smuzhiyun status = "okay"; 125*4882a593Smuzhiyun bus-width = <4>; 126*4882a593Smuzhiyun /* SD1_CD# */ 127*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; 128*4882a593Smuzhiyun no-1-8-v; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* Apalis MMC1 */ 132*4882a593Smuzhiyun mmc@78000400 { 133*4882a593Smuzhiyun status = "okay"; 134*4882a593Smuzhiyun bus-width = <8>; 135*4882a593Smuzhiyun /* MMC1_CD# */ 136*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; 137*4882a593Smuzhiyun no-1-8-v; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ 141*4882a593Smuzhiyun usb@7d000000 { 142*4882a593Smuzhiyun status = "okay"; 143*4882a593Smuzhiyun dr_mode = "otg"; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun usb-phy@7d000000 { 147*4882a593Smuzhiyun status = "okay"; 148*4882a593Smuzhiyun vbus-supply = <®_usbo1_vbus>; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ 152*4882a593Smuzhiyun usb@7d004000 { 153*4882a593Smuzhiyun status = "okay"; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun usb-phy@7d004000 { 157*4882a593Smuzhiyun status = "okay"; 158*4882a593Smuzhiyun vbus-supply = <®_usbh_vbus>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ 162*4882a593Smuzhiyun usb@7d008000 { 163*4882a593Smuzhiyun status = "okay"; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun usb-phy@7d008000 { 167*4882a593Smuzhiyun status = "okay"; 168*4882a593Smuzhiyun vbus-supply = <®_usbh_vbus>; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun backlight: backlight { 172*4882a593Smuzhiyun compatible = "pwm-backlight"; 173*4882a593Smuzhiyun brightness-levels = <255 231 223 207 191 159 127 0>; 174*4882a593Smuzhiyun default-brightness-level = <6>; 175*4882a593Smuzhiyun /* BKL1_ON */ 176*4882a593Smuzhiyun enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 177*4882a593Smuzhiyun power-supply = <®_3v3>; 178*4882a593Smuzhiyun pwms = <&pwm 0 5000000>; /* BKL1_PWM */ 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun gpio-keys { 182*4882a593Smuzhiyun compatible = "gpio-keys"; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun wakeup { 185*4882a593Smuzhiyun label = "WAKE1_MICO"; 186*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; 187*4882a593Smuzhiyun linux,code = <KEY_WAKEUP>; 188*4882a593Smuzhiyun debounce-interval = <10>; 189*4882a593Smuzhiyun wakeup-source; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun panel: panel { 194*4882a593Smuzhiyun /* 195*4882a593Smuzhiyun * edt,et057090dhu: EDT 5.7" LCD TFT 196*4882a593Smuzhiyun * edt,et070080dh6: EDT 7.0" LCD TFT 197*4882a593Smuzhiyun */ 198*4882a593Smuzhiyun compatible = "edt,et057090dhu"; 199*4882a593Smuzhiyun backlight = <&backlight>; 200*4882a593Smuzhiyun power-supply = <®_3v3>; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun reg_3v3: regulator-3v3 { 204*4882a593Smuzhiyun compatible = "regulator-fixed"; 205*4882a593Smuzhiyun regulator-name = "3.3V_SW"; 206*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 207*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun reg_5v0: regulator-5v0 { 211*4882a593Smuzhiyun compatible = "regulator-fixed"; 212*4882a593Smuzhiyun regulator-name = "5V_SW"; 213*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 214*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* USBO1_EN */ 218*4882a593Smuzhiyun reg_usbo1_vbus: regulator-usbo1-vbus { 219*4882a593Smuzhiyun compatible = "regulator-fixed"; 220*4882a593Smuzhiyun regulator-name = "VCC_USBO1"; 221*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 222*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 223*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; 224*4882a593Smuzhiyun enable-active-high; 225*4882a593Smuzhiyun vin-supply = <®_5v0>; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun /* USBH_EN */ 229*4882a593Smuzhiyun reg_usbh_vbus: regulator-usbh-vbus { 230*4882a593Smuzhiyun compatible = "regulator-fixed"; 231*4882a593Smuzhiyun regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; 232*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 233*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 234*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; 235*4882a593Smuzhiyun enable-active-high; 236*4882a593Smuzhiyun vin-supply = <®_5v0>; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun}; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun&gpio { 241*4882a593Smuzhiyun /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ 242*4882a593Smuzhiyun pex-perst-n { 243*4882a593Smuzhiyun gpio-hog; 244*4882a593Smuzhiyun gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>; 245*4882a593Smuzhiyun output-high; 246*4882a593Smuzhiyun line-name = "PEX_PERST_N"; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun}; 249