1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 5*4882a593Smuzhiyun#include "tegra20.dtsi" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun model = "NVIDIA Seaboard"; 9*4882a593Smuzhiyun compatible = "nvidia,seaboard", "nvidia,tegra20"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun aliases { 12*4882a593Smuzhiyun rtc0 = "/i2c@7000d000/tps6586x@34"; 13*4882a593Smuzhiyun rtc1 = "/rtc@7000e000"; 14*4882a593Smuzhiyun serial0 = &uartd; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun chosen { 18*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun memory@0 { 22*4882a593Smuzhiyun reg = <0x00000000 0x40000000>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun host1x@50000000 { 26*4882a593Smuzhiyun dc@54200000 { 27*4882a593Smuzhiyun rgb { 28*4882a593Smuzhiyun status = "okay"; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun nvidia,panel = <&panel>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun hdmi@54280000 { 35*4882a593Smuzhiyun status = "okay"; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun vdd-supply = <&hdmi_vdd_reg>; 38*4882a593Smuzhiyun pll-supply = <&hdmi_pll_reg>; 39*4882a593Smuzhiyun hdmi-supply = <&vdd_hdmi>; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun nvidia,ddc-i2c-bus = <&hdmi_ddc>; 42*4882a593Smuzhiyun nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 43*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun pinmux@70000014 { 48*4882a593Smuzhiyun pinctrl-names = "default"; 49*4882a593Smuzhiyun pinctrl-0 = <&state_default>; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun state_default: pinmux { 52*4882a593Smuzhiyun ata { 53*4882a593Smuzhiyun nvidia,pins = "ata"; 54*4882a593Smuzhiyun nvidia,function = "ide"; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun atb { 57*4882a593Smuzhiyun nvidia,pins = "atb", "gma", "gme"; 58*4882a593Smuzhiyun nvidia,function = "sdio4"; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun atc { 61*4882a593Smuzhiyun nvidia,pins = "atc"; 62*4882a593Smuzhiyun nvidia,function = "nand"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun atd { 65*4882a593Smuzhiyun nvidia,pins = "atd", "ate", "gmb", "spia", 66*4882a593Smuzhiyun "spib", "spic"; 67*4882a593Smuzhiyun nvidia,function = "gmi"; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun cdev1 { 70*4882a593Smuzhiyun nvidia,pins = "cdev1"; 71*4882a593Smuzhiyun nvidia,function = "plla_out"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun cdev2 { 74*4882a593Smuzhiyun nvidia,pins = "cdev2"; 75*4882a593Smuzhiyun nvidia,function = "pllp_out4"; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun crtp { 78*4882a593Smuzhiyun nvidia,pins = "crtp", "lm1"; 79*4882a593Smuzhiyun nvidia,function = "crt"; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun csus { 82*4882a593Smuzhiyun nvidia,pins = "csus"; 83*4882a593Smuzhiyun nvidia,function = "vi_sensor_clk"; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun dap1 { 86*4882a593Smuzhiyun nvidia,pins = "dap1"; 87*4882a593Smuzhiyun nvidia,function = "dap1"; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun dap2 { 90*4882a593Smuzhiyun nvidia,pins = "dap2"; 91*4882a593Smuzhiyun nvidia,function = "dap2"; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun dap3 { 94*4882a593Smuzhiyun nvidia,pins = "dap3"; 95*4882a593Smuzhiyun nvidia,function = "dap3"; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun dap4 { 98*4882a593Smuzhiyun nvidia,pins = "dap4"; 99*4882a593Smuzhiyun nvidia,function = "dap4"; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun dta { 102*4882a593Smuzhiyun nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 103*4882a593Smuzhiyun nvidia,function = "vi"; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun dtf { 106*4882a593Smuzhiyun nvidia,pins = "dtf"; 107*4882a593Smuzhiyun nvidia,function = "i2c3"; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun gmc { 110*4882a593Smuzhiyun nvidia,pins = "gmc"; 111*4882a593Smuzhiyun nvidia,function = "uartd"; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun gmd { 114*4882a593Smuzhiyun nvidia,pins = "gmd"; 115*4882a593Smuzhiyun nvidia,function = "sflash"; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun gpu { 118*4882a593Smuzhiyun nvidia,pins = "gpu"; 119*4882a593Smuzhiyun nvidia,function = "pwm"; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun gpu7 { 122*4882a593Smuzhiyun nvidia,pins = "gpu7"; 123*4882a593Smuzhiyun nvidia,function = "rtck"; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun gpv { 126*4882a593Smuzhiyun nvidia,pins = "gpv", "slxa", "slxk"; 127*4882a593Smuzhiyun nvidia,function = "pcie"; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun hdint { 130*4882a593Smuzhiyun nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", 131*4882a593Smuzhiyun "lsck", "lsda"; 132*4882a593Smuzhiyun nvidia,function = "hdmi"; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun i2cp { 135*4882a593Smuzhiyun nvidia,pins = "i2cp"; 136*4882a593Smuzhiyun nvidia,function = "i2cp"; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun irrx { 139*4882a593Smuzhiyun nvidia,pins = "irrx", "irtx"; 140*4882a593Smuzhiyun nvidia,function = "uartb"; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun kbca { 143*4882a593Smuzhiyun nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 144*4882a593Smuzhiyun "kbce", "kbcf"; 145*4882a593Smuzhiyun nvidia,function = "kbc"; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun lcsn { 148*4882a593Smuzhiyun nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", 149*4882a593Smuzhiyun "lsdi", "lvp0"; 150*4882a593Smuzhiyun nvidia,function = "rsvd4"; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun ld0 { 153*4882a593Smuzhiyun nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 154*4882a593Smuzhiyun "ld5", "ld6", "ld7", "ld8", "ld9", 155*4882a593Smuzhiyun "ld10", "ld11", "ld12", "ld13", "ld14", 156*4882a593Smuzhiyun "ld15", "ld16", "ld17", "ldi", "lhp0", 157*4882a593Smuzhiyun "lhp1", "lhp2", "lhs", "lpp", "lsc0", 158*4882a593Smuzhiyun "lspi", "lvp1", "lvs"; 159*4882a593Smuzhiyun nvidia,function = "displaya"; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun owc { 162*4882a593Smuzhiyun nvidia,pins = "owc", "spdi", "spdo", "uac"; 163*4882a593Smuzhiyun nvidia,function = "rsvd2"; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun pmc { 166*4882a593Smuzhiyun nvidia,pins = "pmc"; 167*4882a593Smuzhiyun nvidia,function = "pwr_on"; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun rm { 170*4882a593Smuzhiyun nvidia,pins = "rm"; 171*4882a593Smuzhiyun nvidia,function = "i2c1"; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun sdb { 174*4882a593Smuzhiyun nvidia,pins = "sdb", "sdc", "sdd"; 175*4882a593Smuzhiyun nvidia,function = "sdio3"; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun sdio1 { 178*4882a593Smuzhiyun nvidia,pins = "sdio1"; 179*4882a593Smuzhiyun nvidia,function = "sdio1"; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun slxc { 182*4882a593Smuzhiyun nvidia,pins = "slxc", "slxd"; 183*4882a593Smuzhiyun nvidia,function = "spdif"; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun spid { 186*4882a593Smuzhiyun nvidia,pins = "spid", "spie", "spif"; 187*4882a593Smuzhiyun nvidia,function = "spi1"; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun spig { 190*4882a593Smuzhiyun nvidia,pins = "spig", "spih"; 191*4882a593Smuzhiyun nvidia,function = "spi2_alt"; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun uaa { 194*4882a593Smuzhiyun nvidia,pins = "uaa", "uab", "uda"; 195*4882a593Smuzhiyun nvidia,function = "ulpi"; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun uad { 198*4882a593Smuzhiyun nvidia,pins = "uad"; 199*4882a593Smuzhiyun nvidia,function = "irda"; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun uca { 202*4882a593Smuzhiyun nvidia,pins = "uca", "ucb"; 203*4882a593Smuzhiyun nvidia,function = "uartc"; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun conf_ata { 206*4882a593Smuzhiyun nvidia,pins = "ata", "atb", "atc", "atd", 207*4882a593Smuzhiyun "cdev1", "cdev2", "dap1", "dap2", 208*4882a593Smuzhiyun "dap4", "ddc", "dtf", "gma", "gmc", "gmd", 209*4882a593Smuzhiyun "gme", "gpu", "gpu7", "i2cp", "irrx", 210*4882a593Smuzhiyun "irtx", "pta", "rm", "sdc", "sdd", 211*4882a593Smuzhiyun "slxd", "slxk", "spdi", "spdo", "uac", 212*4882a593Smuzhiyun "uad", "uca", "ucb", "uda"; 213*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 214*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun conf_ate { 217*4882a593Smuzhiyun nvidia,pins = "ate", "csus", "dap3", 218*4882a593Smuzhiyun "gpv", "owc", "slxc", "spib", "spid", 219*4882a593Smuzhiyun "spie"; 220*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 221*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun conf_ck32 { 224*4882a593Smuzhiyun nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 225*4882a593Smuzhiyun "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 226*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun conf_crtp { 229*4882a593Smuzhiyun nvidia,pins = "crtp", "gmb", "slxa", "spia", 230*4882a593Smuzhiyun "spig", "spih"; 231*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 232*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun conf_dta { 235*4882a593Smuzhiyun nvidia,pins = "dta", "dtb", "dtc", "dtd"; 236*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 237*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun conf_dte { 240*4882a593Smuzhiyun nvidia,pins = "dte", "spif"; 241*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 242*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun conf_hdint { 245*4882a593Smuzhiyun nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 246*4882a593Smuzhiyun "lpw1", "lsc1", "lsck", "lsda", "lsdi", 247*4882a593Smuzhiyun "lvp0"; 248*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun conf_kbca { 251*4882a593Smuzhiyun nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 252*4882a593Smuzhiyun "kbce", "kbcf", "sdio1", "spic", "uaa", 253*4882a593Smuzhiyun "uab"; 254*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 255*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun conf_lc { 258*4882a593Smuzhiyun nvidia,pins = "lc", "ls"; 259*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun conf_ld0 { 262*4882a593Smuzhiyun nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 263*4882a593Smuzhiyun "ld5", "ld6", "ld7", "ld8", "ld9", 264*4882a593Smuzhiyun "ld10", "ld11", "ld12", "ld13", "ld14", 265*4882a593Smuzhiyun "ld15", "ld16", "ld17", "ldi", "lhp0", 266*4882a593Smuzhiyun "lhp1", "lhp2", "lhs", "lm0", "lpp", 267*4882a593Smuzhiyun "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 268*4882a593Smuzhiyun "lvs", "pmc", "sdb"; 269*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun conf_ld17_0 { 272*4882a593Smuzhiyun nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 273*4882a593Smuzhiyun "ld23_22"; 274*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun drive_sdio1 { 277*4882a593Smuzhiyun nvidia,pins = "drive_sdio1"; 278*4882a593Smuzhiyun nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; 279*4882a593Smuzhiyun nvidia,schmitt = <TEGRA_PIN_DISABLE>; 280*4882a593Smuzhiyun nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 281*4882a593Smuzhiyun nvidia,pull-down-strength = <31>; 282*4882a593Smuzhiyun nvidia,pull-up-strength = <31>; 283*4882a593Smuzhiyun nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 284*4882a593Smuzhiyun nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun state_i2cmux_ddc: pinmux_i2cmux_ddc { 289*4882a593Smuzhiyun ddc { 290*4882a593Smuzhiyun nvidia,pins = "ddc"; 291*4882a593Smuzhiyun nvidia,function = "i2c2"; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun pta { 294*4882a593Smuzhiyun nvidia,pins = "pta"; 295*4882a593Smuzhiyun nvidia,function = "rsvd4"; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun }; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun state_i2cmux_pta: pinmux_i2cmux_pta { 300*4882a593Smuzhiyun ddc { 301*4882a593Smuzhiyun nvidia,pins = "ddc"; 302*4882a593Smuzhiyun nvidia,function = "rsvd4"; 303*4882a593Smuzhiyun }; 304*4882a593Smuzhiyun pta { 305*4882a593Smuzhiyun nvidia,pins = "pta"; 306*4882a593Smuzhiyun nvidia,function = "i2c2"; 307*4882a593Smuzhiyun }; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun state_i2cmux_idle: pinmux_i2cmux_idle { 311*4882a593Smuzhiyun ddc { 312*4882a593Smuzhiyun nvidia,pins = "ddc"; 313*4882a593Smuzhiyun nvidia,function = "rsvd4"; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun pta { 316*4882a593Smuzhiyun nvidia,pins = "pta"; 317*4882a593Smuzhiyun nvidia,function = "rsvd4"; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun }; 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun i2s@70002800 { 323*4882a593Smuzhiyun status = "okay"; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun serial@70006300 { 327*4882a593Smuzhiyun status = "okay"; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun pwm: pwm@7000a000 { 331*4882a593Smuzhiyun status = "okay"; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun i2c@7000c000 { 335*4882a593Smuzhiyun status = "okay"; 336*4882a593Smuzhiyun clock-frequency = <400000>; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun wm8903: wm8903@1a { 339*4882a593Smuzhiyun compatible = "wlf,wm8903"; 340*4882a593Smuzhiyun reg = <0x1a>; 341*4882a593Smuzhiyun interrupt-parent = <&gpio>; 342*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun gpio-controller; 345*4882a593Smuzhiyun #gpio-cells = <2>; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun micdet-cfg = <0>; 348*4882a593Smuzhiyun micdet-delay = <100>; 349*4882a593Smuzhiyun gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; 350*4882a593Smuzhiyun }; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun /* ALS and proximity sensor */ 353*4882a593Smuzhiyun isl29018@44 { 354*4882a593Smuzhiyun compatible = "isil,isl29018"; 355*4882a593Smuzhiyun reg = <0x44>; 356*4882a593Smuzhiyun interrupt-parent = <&gpio>; 357*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; 358*4882a593Smuzhiyun }; 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun gyrometer@68 { 361*4882a593Smuzhiyun compatible = "invn,mpu3050"; 362*4882a593Smuzhiyun reg = <0x68>; 363*4882a593Smuzhiyun interrupt-parent = <&gpio>; 364*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>; 365*4882a593Smuzhiyun }; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun i2c@7000c400 { 369*4882a593Smuzhiyun status = "okay"; 370*4882a593Smuzhiyun clock-frequency = <100000>; 371*4882a593Smuzhiyun }; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun i2cmux { 374*4882a593Smuzhiyun compatible = "i2c-mux-pinctrl"; 375*4882a593Smuzhiyun #address-cells = <1>; 376*4882a593Smuzhiyun #size-cells = <0>; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun i2c-parent = <&{/i2c@7000c400}>; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun pinctrl-names = "ddc", "pta", "idle"; 381*4882a593Smuzhiyun pinctrl-0 = <&state_i2cmux_ddc>; 382*4882a593Smuzhiyun pinctrl-1 = <&state_i2cmux_pta>; 383*4882a593Smuzhiyun pinctrl-2 = <&state_i2cmux_idle>; 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun hdmi_ddc: i2c@0 { 386*4882a593Smuzhiyun reg = <0>; 387*4882a593Smuzhiyun #address-cells = <1>; 388*4882a593Smuzhiyun #size-cells = <0>; 389*4882a593Smuzhiyun }; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun lvds_ddc: i2c@1 { 392*4882a593Smuzhiyun reg = <1>; 393*4882a593Smuzhiyun #address-cells = <1>; 394*4882a593Smuzhiyun #size-cells = <0>; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun smart-battery@b { 397*4882a593Smuzhiyun compatible = "ti,bq20z75", "sbs,sbs-battery"; 398*4882a593Smuzhiyun reg = <0xb>; 399*4882a593Smuzhiyun sbs,i2c-retry-count = <2>; 400*4882a593Smuzhiyun sbs,poll-retry-count = <10>; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun i2c@7000c500 { 406*4882a593Smuzhiyun status = "okay"; 407*4882a593Smuzhiyun clock-frequency = <400000>; 408*4882a593Smuzhiyun }; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun i2c@7000d000 { 411*4882a593Smuzhiyun status = "okay"; 412*4882a593Smuzhiyun clock-frequency = <400000>; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun magnetometer@c { 415*4882a593Smuzhiyun compatible = "asahi-kasei,ak8975"; 416*4882a593Smuzhiyun reg = <0xc>; 417*4882a593Smuzhiyun interrupt-parent = <&gpio>; 418*4882a593Smuzhiyun interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; 419*4882a593Smuzhiyun }; 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun pmic: tps6586x@34 { 422*4882a593Smuzhiyun compatible = "ti,tps6586x"; 423*4882a593Smuzhiyun reg = <0x34>; 424*4882a593Smuzhiyun interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun ti,system-power-controller; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun #gpio-cells = <2>; 429*4882a593Smuzhiyun gpio-controller; 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun sys-supply = <&vdd_5v0_reg>; 432*4882a593Smuzhiyun vin-sm0-supply = <&sys_reg>; 433*4882a593Smuzhiyun vin-sm1-supply = <&sys_reg>; 434*4882a593Smuzhiyun vin-sm2-supply = <&sys_reg>; 435*4882a593Smuzhiyun vinldo01-supply = <&sm2_reg>; 436*4882a593Smuzhiyun vinldo23-supply = <&sm2_reg>; 437*4882a593Smuzhiyun vinldo4-supply = <&sm2_reg>; 438*4882a593Smuzhiyun vinldo678-supply = <&sm2_reg>; 439*4882a593Smuzhiyun vinldo9-supply = <&sm2_reg>; 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun regulators { 442*4882a593Smuzhiyun sys_reg: sys { 443*4882a593Smuzhiyun regulator-name = "vdd_sys"; 444*4882a593Smuzhiyun regulator-always-on; 445*4882a593Smuzhiyun }; 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun sm0 { 448*4882a593Smuzhiyun regulator-name = "vdd_sm0,vdd_core"; 449*4882a593Smuzhiyun regulator-min-microvolt = <1300000>; 450*4882a593Smuzhiyun regulator-max-microvolt = <1300000>; 451*4882a593Smuzhiyun regulator-always-on; 452*4882a593Smuzhiyun }; 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun sm1 { 455*4882a593Smuzhiyun regulator-name = "vdd_sm1,vdd_cpu"; 456*4882a593Smuzhiyun regulator-min-microvolt = <1125000>; 457*4882a593Smuzhiyun regulator-max-microvolt = <1125000>; 458*4882a593Smuzhiyun regulator-always-on; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun sm2_reg: sm2 { 462*4882a593Smuzhiyun regulator-name = "vdd_sm2,vin_ldo*"; 463*4882a593Smuzhiyun regulator-min-microvolt = <3700000>; 464*4882a593Smuzhiyun regulator-max-microvolt = <3700000>; 465*4882a593Smuzhiyun regulator-always-on; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun /* LDO0 is not connected to anything */ 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun ldo1 { 471*4882a593Smuzhiyun regulator-name = "vdd_ldo1,avdd_pll*"; 472*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 473*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 474*4882a593Smuzhiyun regulator-always-on; 475*4882a593Smuzhiyun }; 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun ldo2 { 478*4882a593Smuzhiyun regulator-name = "vdd_ldo2,vdd_rtc"; 479*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 480*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 481*4882a593Smuzhiyun }; 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun ldo3 { 484*4882a593Smuzhiyun regulator-name = "vdd_ldo3,avdd_usb*"; 485*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 486*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 487*4882a593Smuzhiyun regulator-always-on; 488*4882a593Smuzhiyun }; 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun ldo4 { 491*4882a593Smuzhiyun regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 492*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 493*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 494*4882a593Smuzhiyun regulator-always-on; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun ldo5 { 498*4882a593Smuzhiyun regulator-name = "vdd_ldo5,vcore_mmc"; 499*4882a593Smuzhiyun regulator-min-microvolt = <2850000>; 500*4882a593Smuzhiyun regulator-max-microvolt = <2850000>; 501*4882a593Smuzhiyun regulator-always-on; 502*4882a593Smuzhiyun }; 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun ldo6 { 505*4882a593Smuzhiyun regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; 506*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 507*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 508*4882a593Smuzhiyun }; 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun hdmi_vdd_reg: ldo7 { 511*4882a593Smuzhiyun regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; 512*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 513*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 514*4882a593Smuzhiyun }; 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun hdmi_pll_reg: ldo8 { 517*4882a593Smuzhiyun regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 518*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 519*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun ldo9 { 523*4882a593Smuzhiyun regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; 524*4882a593Smuzhiyun regulator-min-microvolt = <2850000>; 525*4882a593Smuzhiyun regulator-max-microvolt = <2850000>; 526*4882a593Smuzhiyun regulator-always-on; 527*4882a593Smuzhiyun }; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun ldo_rtc { 530*4882a593Smuzhiyun regulator-name = "vdd_rtc_out,vdd_cell"; 531*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 532*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 533*4882a593Smuzhiyun regulator-always-on; 534*4882a593Smuzhiyun }; 535*4882a593Smuzhiyun }; 536*4882a593Smuzhiyun }; 537*4882a593Smuzhiyun 538*4882a593Smuzhiyun temperature-sensor@4c { 539*4882a593Smuzhiyun compatible = "onnn,nct1008"; 540*4882a593Smuzhiyun reg = <0x4c>; 541*4882a593Smuzhiyun }; 542*4882a593Smuzhiyun }; 543*4882a593Smuzhiyun 544*4882a593Smuzhiyun kbc@7000e200 { 545*4882a593Smuzhiyun status = "okay"; 546*4882a593Smuzhiyun nvidia,debounce-delay-ms = <32>; 547*4882a593Smuzhiyun nvidia,repeat-delay-ms = <160>; 548*4882a593Smuzhiyun nvidia,ghost-filter; 549*4882a593Smuzhiyun nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; 550*4882a593Smuzhiyun nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; 551*4882a593Smuzhiyun linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W) 552*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x03, KEY_S) 553*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x04, KEY_A) 554*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x05, KEY_Z) 555*4882a593Smuzhiyun MATRIX_KEY(0x00, 0x07, KEY_FN) 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA) 558*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT) 559*4882a593Smuzhiyun MATRIX_KEY(0x02, 0x07, KEY_LEFTALT) 560*4882a593Smuzhiyun 561*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x00, KEY_5) 562*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x01, KEY_4) 563*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x02, KEY_R) 564*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x03, KEY_E) 565*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x04, KEY_F) 566*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x05, KEY_D) 567*4882a593Smuzhiyun MATRIX_KEY(0x03, 0x06, KEY_X) 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x00, KEY_7) 570*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x01, KEY_6) 571*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x02, KEY_T) 572*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x03, KEY_H) 573*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x04, KEY_G) 574*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x05, KEY_V) 575*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x06, KEY_C) 576*4882a593Smuzhiyun MATRIX_KEY(0x04, 0x07, KEY_SPACE) 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x00, KEY_9) 579*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x01, KEY_8) 580*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x02, KEY_U) 581*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x03, KEY_Y) 582*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x04, KEY_J) 583*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x05, KEY_N) 584*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x06, KEY_B) 585*4882a593Smuzhiyun MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH) 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x00, KEY_MINUS) 588*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x01, KEY_0) 589*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x02, KEY_O) 590*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x03, KEY_I) 591*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x04, KEY_L) 592*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x05, KEY_K) 593*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x06, KEY_COMMA) 594*4882a593Smuzhiyun MATRIX_KEY(0x06, 0x07, KEY_M) 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x01, KEY_EQUAL) 597*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE) 598*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x03, KEY_ENTER) 599*4882a593Smuzhiyun MATRIX_KEY(0x07, 0x07, KEY_MENU) 600*4882a593Smuzhiyun 601*4882a593Smuzhiyun MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT) 602*4882a593Smuzhiyun MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT) 603*4882a593Smuzhiyun 604*4882a593Smuzhiyun MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL) 605*4882a593Smuzhiyun MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL) 606*4882a593Smuzhiyun 607*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE) 608*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x01, KEY_P) 609*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE) 610*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON) 611*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x04, KEY_SLASH) 612*4882a593Smuzhiyun MATRIX_KEY(0x0B, 0x05, KEY_DOT) 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x00, KEY_F10) 615*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x01, KEY_F9) 616*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE) 617*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x03, KEY_3) 618*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x04, KEY_2) 619*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x05, KEY_UP) 620*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x06, KEY_PRINT) 621*4882a593Smuzhiyun MATRIX_KEY(0x0C, 0x07, KEY_PAUSE) 622*4882a593Smuzhiyun 623*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x00, KEY_INSERT) 624*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x01, KEY_DELETE) 625*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP ) 626*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN) 627*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x05, KEY_RIGHT) 628*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x06, KEY_DOWN) 629*4882a593Smuzhiyun MATRIX_KEY(0x0D, 0x07, KEY_LEFT) 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x00, KEY_F11) 632*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x01, KEY_F12) 633*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x02, KEY_F8) 634*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x03, KEY_Q) 635*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x04, KEY_F4) 636*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x05, KEY_F3) 637*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x06, KEY_1) 638*4882a593Smuzhiyun MATRIX_KEY(0x0E, 0x07, KEY_F7) 639*4882a593Smuzhiyun 640*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x00, KEY_ESC) 641*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x01, KEY_GRAVE) 642*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x02, KEY_F5) 643*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x03, KEY_TAB) 644*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x04, KEY_F1) 645*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x05, KEY_F2) 646*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK) 647*4882a593Smuzhiyun MATRIX_KEY(0x0F, 0x07, KEY_F6) 648*4882a593Smuzhiyun 649*4882a593Smuzhiyun /* Software Handled Function Keys */ 650*4882a593Smuzhiyun MATRIX_KEY(0x14, 0x00, KEY_KP7) 651*4882a593Smuzhiyun 652*4882a593Smuzhiyun MATRIX_KEY(0x15, 0x00, KEY_KP9) 653*4882a593Smuzhiyun MATRIX_KEY(0x15, 0x01, KEY_KP8) 654*4882a593Smuzhiyun MATRIX_KEY(0x15, 0x02, KEY_KP4) 655*4882a593Smuzhiyun MATRIX_KEY(0x15, 0x04, KEY_KP1) 656*4882a593Smuzhiyun 657*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x01, KEY_KPSLASH) 658*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x02, KEY_KP6) 659*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x03, KEY_KP5) 660*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x04, KEY_KP3) 661*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x05, KEY_KP2) 662*4882a593Smuzhiyun MATRIX_KEY(0x16, 0x07, KEY_KP0) 663*4882a593Smuzhiyun 664*4882a593Smuzhiyun MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK) 665*4882a593Smuzhiyun MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS) 666*4882a593Smuzhiyun MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS) 667*4882a593Smuzhiyun MATRIX_KEY(0x1B, 0x05, KEY_KPDOT) 668*4882a593Smuzhiyun 669*4882a593Smuzhiyun MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP) 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x03, KEY_HOME) 672*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x04, KEY_END) 673*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN) 674*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN) 675*4882a593Smuzhiyun MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP) 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK) 678*4882a593Smuzhiyun MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK) 679*4882a593Smuzhiyun MATRIX_KEY(0x1E, 0x02, KEY_MUTE) 680*4882a593Smuzhiyun 681*4882a593Smuzhiyun MATRIX_KEY(0x1F, 0x04, KEY_HELP)>; 682*4882a593Smuzhiyun }; 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun pmc@7000e400 { 685*4882a593Smuzhiyun nvidia,invert-interrupt; 686*4882a593Smuzhiyun nvidia,suspend-mode = <1>; 687*4882a593Smuzhiyun nvidia,cpu-pwr-good-time = <5000>; 688*4882a593Smuzhiyun nvidia,cpu-pwr-off-time = <5000>; 689*4882a593Smuzhiyun nvidia,core-pwr-good-time = <3845 3845>; 690*4882a593Smuzhiyun nvidia,core-pwr-off-time = <3875>; 691*4882a593Smuzhiyun nvidia,sys-clock-req-active-high; 692*4882a593Smuzhiyun }; 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun memory-controller@7000f400 { 695*4882a593Smuzhiyun emc-table@190000 { 696*4882a593Smuzhiyun reg = <190000>; 697*4882a593Smuzhiyun compatible = "nvidia,tegra20-emc-table"; 698*4882a593Smuzhiyun clock-frequency = <190000>; 699*4882a593Smuzhiyun nvidia,emc-registers = <0x0000000c 0x00000026 700*4882a593Smuzhiyun 0x00000009 0x00000003 0x00000004 0x00000004 701*4882a593Smuzhiyun 0x00000002 0x0000000c 0x00000003 0x00000003 702*4882a593Smuzhiyun 0x00000002 0x00000001 0x00000004 0x00000005 703*4882a593Smuzhiyun 0x00000004 0x00000009 0x0000000d 0x0000059f 704*4882a593Smuzhiyun 0x00000000 0x00000003 0x00000003 0x00000003 705*4882a593Smuzhiyun 0x00000003 0x00000001 0x0000000b 0x000000c8 706*4882a593Smuzhiyun 0x00000003 0x00000007 0x00000004 0x0000000f 707*4882a593Smuzhiyun 0x00000002 0x00000000 0x00000000 0x00000002 708*4882a593Smuzhiyun 0x00000000 0x00000000 0x00000083 0xa06204ae 709*4882a593Smuzhiyun 0x007dc010 0x00000000 0x00000000 0x00000000 710*4882a593Smuzhiyun 0x00000000 0x00000000 0x00000000 0x00000000>; 711*4882a593Smuzhiyun }; 712*4882a593Smuzhiyun 713*4882a593Smuzhiyun emc-table@380000 { 714*4882a593Smuzhiyun reg = <380000>; 715*4882a593Smuzhiyun compatible = "nvidia,tegra20-emc-table"; 716*4882a593Smuzhiyun clock-frequency = <380000>; 717*4882a593Smuzhiyun nvidia,emc-registers = <0x00000017 0x0000004b 718*4882a593Smuzhiyun 0x00000012 0x00000006 0x00000004 0x00000005 719*4882a593Smuzhiyun 0x00000003 0x0000000c 0x00000006 0x00000006 720*4882a593Smuzhiyun 0x00000003 0x00000001 0x00000004 0x00000005 721*4882a593Smuzhiyun 0x00000004 0x00000009 0x0000000d 0x00000b5f 722*4882a593Smuzhiyun 0x00000000 0x00000003 0x00000003 0x00000006 723*4882a593Smuzhiyun 0x00000006 0x00000001 0x00000011 0x000000c8 724*4882a593Smuzhiyun 0x00000003 0x0000000e 0x00000007 0x0000000f 725*4882a593Smuzhiyun 0x00000002 0x00000000 0x00000000 0x00000002 726*4882a593Smuzhiyun 0x00000000 0x00000000 0x00000083 0xe044048b 727*4882a593Smuzhiyun 0x007d8010 0x00000000 0x00000000 0x00000000 728*4882a593Smuzhiyun 0x00000000 0x00000000 0x00000000 0x00000000>; 729*4882a593Smuzhiyun }; 730*4882a593Smuzhiyun }; 731*4882a593Smuzhiyun 732*4882a593Smuzhiyun usb@c5000000 { 733*4882a593Smuzhiyun status = "okay"; 734*4882a593Smuzhiyun dr_mode = "otg"; 735*4882a593Smuzhiyun }; 736*4882a593Smuzhiyun 737*4882a593Smuzhiyun usb-phy@c5000000 { 738*4882a593Smuzhiyun status = "okay"; 739*4882a593Smuzhiyun vbus-supply = <&vbus_reg>; 740*4882a593Smuzhiyun dr_mode = "otg"; 741*4882a593Smuzhiyun }; 742*4882a593Smuzhiyun 743*4882a593Smuzhiyun usb@c5004000 { 744*4882a593Smuzhiyun status = "okay"; 745*4882a593Smuzhiyun nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 746*4882a593Smuzhiyun GPIO_ACTIVE_LOW>; 747*4882a593Smuzhiyun }; 748*4882a593Smuzhiyun 749*4882a593Smuzhiyun usb-phy@c5004000 { 750*4882a593Smuzhiyun status = "okay"; 751*4882a593Smuzhiyun nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 752*4882a593Smuzhiyun GPIO_ACTIVE_LOW>; 753*4882a593Smuzhiyun }; 754*4882a593Smuzhiyun 755*4882a593Smuzhiyun usb@c5008000 { 756*4882a593Smuzhiyun status = "okay"; 757*4882a593Smuzhiyun }; 758*4882a593Smuzhiyun 759*4882a593Smuzhiyun usb-phy@c5008000 { 760*4882a593Smuzhiyun status = "okay"; 761*4882a593Smuzhiyun }; 762*4882a593Smuzhiyun 763*4882a593Smuzhiyun mmc@c8000000 { 764*4882a593Smuzhiyun status = "okay"; 765*4882a593Smuzhiyun power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; 766*4882a593Smuzhiyun bus-width = <4>; 767*4882a593Smuzhiyun keep-power-in-suspend; 768*4882a593Smuzhiyun }; 769*4882a593Smuzhiyun 770*4882a593Smuzhiyun mmc@c8000400 { 771*4882a593Smuzhiyun status = "okay"; 772*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 773*4882a593Smuzhiyun wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 774*4882a593Smuzhiyun power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 775*4882a593Smuzhiyun bus-width = <4>; 776*4882a593Smuzhiyun }; 777*4882a593Smuzhiyun 778*4882a593Smuzhiyun mmc@c8000600 { 779*4882a593Smuzhiyun status = "okay"; 780*4882a593Smuzhiyun bus-width = <8>; 781*4882a593Smuzhiyun non-removable; 782*4882a593Smuzhiyun }; 783*4882a593Smuzhiyun 784*4882a593Smuzhiyun backlight: backlight { 785*4882a593Smuzhiyun compatible = "pwm-backlight"; 786*4882a593Smuzhiyun 787*4882a593Smuzhiyun enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; 788*4882a593Smuzhiyun power-supply = <&vdd_bl_reg>; 789*4882a593Smuzhiyun pwms = <&pwm 2 5000000>; 790*4882a593Smuzhiyun 791*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 792*4882a593Smuzhiyun default-brightness-level = <6>; 793*4882a593Smuzhiyun }; 794*4882a593Smuzhiyun 795*4882a593Smuzhiyun clk32k_in: clock@0 { 796*4882a593Smuzhiyun compatible = "fixed-clock"; 797*4882a593Smuzhiyun clock-frequency = <32768>; 798*4882a593Smuzhiyun #clock-cells = <0>; 799*4882a593Smuzhiyun }; 800*4882a593Smuzhiyun 801*4882a593Smuzhiyun gpio-keys { 802*4882a593Smuzhiyun compatible = "gpio-keys"; 803*4882a593Smuzhiyun 804*4882a593Smuzhiyun power { 805*4882a593Smuzhiyun label = "Power"; 806*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 807*4882a593Smuzhiyun linux,code = <KEY_POWER>; 808*4882a593Smuzhiyun wakeup-source; 809*4882a593Smuzhiyun }; 810*4882a593Smuzhiyun 811*4882a593Smuzhiyun lid { 812*4882a593Smuzhiyun label = "Lid"; 813*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; 814*4882a593Smuzhiyun linux,input-type = <5>; /* EV_SW */ 815*4882a593Smuzhiyun linux,code = <0>; /* SW_LID */ 816*4882a593Smuzhiyun debounce-interval = <1>; 817*4882a593Smuzhiyun wakeup-source; 818*4882a593Smuzhiyun }; 819*4882a593Smuzhiyun }; 820*4882a593Smuzhiyun 821*4882a593Smuzhiyun panel: panel { 822*4882a593Smuzhiyun compatible = "chunghwa,claa101wa01a"; 823*4882a593Smuzhiyun 824*4882a593Smuzhiyun power-supply = <&vdd_pnl_reg>; 825*4882a593Smuzhiyun enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; 826*4882a593Smuzhiyun 827*4882a593Smuzhiyun backlight = <&backlight>; 828*4882a593Smuzhiyun ddc-i2c-bus = <&lvds_ddc>; 829*4882a593Smuzhiyun }; 830*4882a593Smuzhiyun 831*4882a593Smuzhiyun vdd_5v0_reg: regulator@0 { 832*4882a593Smuzhiyun compatible = "regulator-fixed"; 833*4882a593Smuzhiyun regulator-name = "vdd_5v0"; 834*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 835*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 836*4882a593Smuzhiyun regulator-always-on; 837*4882a593Smuzhiyun }; 838*4882a593Smuzhiyun 839*4882a593Smuzhiyun regulator@1 { 840*4882a593Smuzhiyun compatible = "regulator-fixed"; 841*4882a593Smuzhiyun regulator-name = "vdd_1v5"; 842*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 843*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 844*4882a593Smuzhiyun gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; 845*4882a593Smuzhiyun }; 846*4882a593Smuzhiyun 847*4882a593Smuzhiyun regulator@2 { 848*4882a593Smuzhiyun compatible = "regulator-fixed"; 849*4882a593Smuzhiyun regulator-name = "vdd_1v2"; 850*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 851*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 852*4882a593Smuzhiyun gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; 853*4882a593Smuzhiyun enable-active-high; 854*4882a593Smuzhiyun }; 855*4882a593Smuzhiyun 856*4882a593Smuzhiyun vbus_reg: regulator@3 { 857*4882a593Smuzhiyun compatible = "regulator-fixed"; 858*4882a593Smuzhiyun regulator-name = "vdd_vbus_wup1"; 859*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 860*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 861*4882a593Smuzhiyun enable-active-high; 862*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(D, 0) 0>; 863*4882a593Smuzhiyun regulator-always-on; 864*4882a593Smuzhiyun regulator-boot-on; 865*4882a593Smuzhiyun }; 866*4882a593Smuzhiyun 867*4882a593Smuzhiyun vdd_pnl_reg: regulator@4 { 868*4882a593Smuzhiyun compatible = "regulator-fixed"; 869*4882a593Smuzhiyun regulator-name = "vdd_pnl"; 870*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 871*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 872*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; 873*4882a593Smuzhiyun enable-active-high; 874*4882a593Smuzhiyun }; 875*4882a593Smuzhiyun 876*4882a593Smuzhiyun vdd_bl_reg: regulator@5 { 877*4882a593Smuzhiyun compatible = "regulator-fixed"; 878*4882a593Smuzhiyun regulator-name = "vdd_bl"; 879*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 880*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 881*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; 882*4882a593Smuzhiyun enable-active-high; 883*4882a593Smuzhiyun }; 884*4882a593Smuzhiyun 885*4882a593Smuzhiyun vdd_hdmi: regulator@6 { 886*4882a593Smuzhiyun compatible = "regulator-fixed"; 887*4882a593Smuzhiyun regulator-name = "VDDIO_HDMI"; 888*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 889*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 890*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; 891*4882a593Smuzhiyun enable-active-high; 892*4882a593Smuzhiyun vin-supply = <&vdd_5v0_reg>; 893*4882a593Smuzhiyun }; 894*4882a593Smuzhiyun 895*4882a593Smuzhiyun sound { 896*4882a593Smuzhiyun compatible = "nvidia,tegra-audio-wm8903-seaboard", 897*4882a593Smuzhiyun "nvidia,tegra-audio-wm8903"; 898*4882a593Smuzhiyun nvidia,model = "NVIDIA Tegra Seaboard"; 899*4882a593Smuzhiyun 900*4882a593Smuzhiyun nvidia,audio-routing = 901*4882a593Smuzhiyun "Headphone Jack", "HPOUTR", 902*4882a593Smuzhiyun "Headphone Jack", "HPOUTL", 903*4882a593Smuzhiyun "Int Spk", "ROP", 904*4882a593Smuzhiyun "Int Spk", "RON", 905*4882a593Smuzhiyun "Int Spk", "LOP", 906*4882a593Smuzhiyun "Int Spk", "LON", 907*4882a593Smuzhiyun "Mic Jack", "MICBIAS", 908*4882a593Smuzhiyun "IN1R", "Mic Jack"; 909*4882a593Smuzhiyun 910*4882a593Smuzhiyun nvidia,i2s-controller = <&tegra_i2s1>; 911*4882a593Smuzhiyun nvidia,audio-codec = <&wm8903>; 912*4882a593Smuzhiyun 913*4882a593Smuzhiyun nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 914*4882a593Smuzhiyun nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>; 915*4882a593Smuzhiyun 916*4882a593Smuzhiyun clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 917*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 918*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_CDEV1>; 919*4882a593Smuzhiyun clock-names = "pll_a", "pll_a_out0", "mclk"; 920*4882a593Smuzhiyun }; 921*4882a593Smuzhiyun}; 922